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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-02 04:41:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-02 04:41:37 -0700 |
| commit | 1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f (patch) | |
| tree | 823a31838ece3f9a273bbca2151c335dae63da9f /env | |
| parent | be72d6bacf1a14b85b142092bc47e4bfe68b38fd (diff) | |
| download | riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.zip riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.tar.gz riscv-tests-1dd1e13180dd65ffe3075cbdc5c12fda8c3e755f.tar.bz2 | |
use RVTEST_RV64UF macro for FPU tests
Diffstat (limited to 'env')
| -rw-r--r-- | env/p/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/pm/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/pt/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/v/riscv_test.h | 14 |
4 files changed, 22 insertions, 4 deletions
diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h index 8ce8490..a537fb2 100644 --- a/env/p/riscv_test.h +++ b/env/p/riscv_test.h @@ -7,6 +7,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_RV32U \ clearpcr cr0, 0x80 diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h index fd07ead..98d0580 100644 --- a/env/pm/riscv_test.h +++ b/env/pm/riscv_test.h @@ -7,6 +7,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_RV64S \ #define RVTEST_FP_ENABLE \ diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h index 363e6e1..748fe97 100644 --- a/env/pt/riscv_test.h +++ b/env/pt/riscv_test.h @@ -9,6 +9,10 @@ #define RVTEST_RV64U \ +#define RVTEST_RV64UF \ + RVTEST_RV64U; \ + RVTEST_FP_ENABLE + #define RVTEST_FP_ENABLE \ setpcr cr0, 2; \ mfpcr a0, cr0; \ diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h index 2a1710d..6aa232e 100644 --- a/env/v/riscv_test.h +++ b/env/v/riscv_test.h @@ -6,11 +6,17 @@ //----------------------------------------------------------------------- #define RVTEST_RV64U \ + .text; \ +init: \ + ret -#define RVTEST_RV64S \ - -#define RVTEST_FP_ENABLE \ +#define RVTEST_RV64UF \ + .text; \ +init: \ mtfsr x0; \ + ret + +#define RVTEST_RV64S \ #define RVTEST_VEC_ENABLE \ mfpcr t0, cr0; \ @@ -24,7 +30,7 @@ .align 13; \ .global userstart; \ userstart: \ - RVTEST_FP_ENABLE; \ + jal init //----------------------------------------------------------------------- // End Macro |