diff options
author | Tim Newsome <tim@sifive.com> | 2022-10-21 09:23:36 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-10-21 09:23:36 -0700 |
commit | 7e77eedc514a6538e07b666c36449e54080054b7 (patch) | |
tree | 69bc3364de7a87659287db016c3b9ac8787f551b /debug | |
parent | 1d03f2a827f2a37f7d7b65218ef679fbafc797da (diff) | |
download | riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.zip riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.tar.gz riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.tar.bz2 |
Change memory address used in debug tests. (#422)
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.
Diffstat (limited to 'debug')
-rw-r--r-- | debug/bin/README.md | 2 | ||||
-rw-r--r-- | debug/bin/RTOSDemo32.axf | bin | 131616 -> 131544 bytes | |||
-rwxr-xr-x | debug/targets/RISC-V/spike32.lds | 2 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32.py | 2 |
4 files changed, 3 insertions, 3 deletions
diff --git a/debug/bin/README.md b/debug/bin/README.md index 7e81515..39576a2 100644 --- a/debug/bin/README.md +++ b/debug/bin/README.md @@ -3,5 +3,5 @@ This directory contains binaries that are not easy to compile. RTOSDemo32.axf and RTOSDemo64.axf are created by checking out https://github.com/FreeRTOS/FreeRTOS, following the instructions in `FreeRTOS/Demo/RISC-V-spike-htif_GCC/README.md`, and building: -* `make XLEN=32 BASE_ADDRESS=0x10000000` +* `make XLEN=32 BASE_ADDRESS=0x10100000` * `make XLEN=64 BASE_ADDRESS=0x1212340000` diff --git a/debug/bin/RTOSDemo32.axf b/debug/bin/RTOSDemo32.axf Binary files differindex 5fa3fe7..88d49f4 100644 --- a/debug/bin/RTOSDemo32.axf +++ b/debug/bin/RTOSDemo32.axf diff --git a/debug/targets/RISC-V/spike32.lds b/debug/targets/RISC-V/spike32.lds index 84216db..77bb1ba 100755 --- a/debug/targets/RISC-V/spike32.lds +++ b/debug/targets/RISC-V/spike32.lds @@ -4,7 +4,7 @@ SECTIONS { /* Leave some space for pk's data structures, which includes tohost/fromhost * which are special addresses we ought to leave alone. */ - . = 0x10010000; + . = 0x10110000; .text : { *(.text.entry) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 17d28fb..0d67ebd 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -3,7 +3,7 @@ import testlib class spike32_hart(targets.Hart): xlen = 32 - ram = 0x10000000 + ram = 0x10100000 ram_size = 0x10000000 bad_address = ram - 8 instruction_hardware_breakpoint_count = 4 |