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| author | Tim Newsome <tim@sifive.com> | 2019-07-15 10:30:06 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-15 10:30:06 -0700 |
| commit | 92862bcb27a53f246126c95203b44153d324bbd7 (patch) | |
| tree | c75969e882b8801416b9b6582518dd10ce08cc8f /debug/targets/RISC-V | |
| parent | fad99cec99c30a1ef79d0daa53bbd796c632e538 (diff) | |
| download | riscv-tests-92862bcb27a53f246126c95203b44153d324bbd7.zip riscv-tests-92862bcb27a53f246126c95203b44153d324bbd7.tar.gz riscv-tests-92862bcb27a53f246126c95203b44153d324bbd7.tar.bz2 | |
Use work area in spike-1 to cover CRC algorithm. (#195)
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index 6f7da74..5a76a31 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -9,6 +9,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 + gdb_report_data_abort enable gdb_report_register_access_error enable |