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| author | Tim Newsome <tim@sifive.com> | 2018-08-27 13:17:51 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-08-29 15:00:23 -0700 |
| commit | 4dddbc79ada7f0a836cf538676c57c8df103ccf6 (patch) | |
| tree | 7c22387fa778244eef8ff1d30a55ffb005b09fea /debug/targets/RISC-V/spike32.py | |
| parent | 40dbc5118c9ac4beb4fc0a28cf4ad4cb56536111 (diff) | |
| download | riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.zip riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.tar.gz riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.tar.bz2 | |
Add test case for `riscv expose_custom`.
Only works against spike, where I've implemented some custom debug
registers to test against.
Diffstat (limited to 'debug/targets/RISC-V/spike32.py')
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index dfcfc01..a831ecb 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -13,6 +13,7 @@ class spike32(targets.Target): harts = [spike32_hart()] openocd_config_path = "spike-1.cfg" timeout_sec = 30 + implements_custom_test = True def create(self): # 64-bit FPRs on 32-bit target |