From 4dddbc79ada7f0a836cf538676c57c8df103ccf6 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 27 Aug 2018 13:17:51 -0700 Subject: Add test case for `riscv expose_custom`. Only works against spike, where I've implemented some custom debug registers to test against. --- debug/targets/RISC-V/spike32.py | 1 + 1 file changed, 1 insertion(+) (limited to 'debug/targets/RISC-V/spike32.py') diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index dfcfc01..a831ecb 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -13,6 +13,7 @@ class spike32(targets.Target): harts = [spike32_hart()] openocd_config_path = "spike-1.cfg" timeout_sec = 30 + implements_custom_test = True def create(self): # 64-bit FPRs on 32-bit target -- cgit v1.1