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| author | Tim Newsome <tim@sifive.com> | 2016-10-31 13:30:44 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-10-31 13:30:44 -0700 |
| commit | ce405b436277a52f764aa15551603e6dce3f568f (patch) | |
| tree | 8bd4e6a253e2752c388e80498c6295ae21767275 /debug/targets.py | |
| parent | f204b5c2b6b8914060614cd77ea10509968c3fa4 (diff) | |
| download | riscv-tests-ce405b436277a52f764aa15551603e6dce3f568f.zip riscv-tests-ce405b436277a52f764aa15551603e6dce3f568f.tar.gz riscv-tests-ce405b436277a52f764aa15551603e6dce3f568f.tar.bz2 | |
Add basic floating point register test.
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index 3cf9728..ca075ec 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -41,6 +41,7 @@ class Target(object): testlib.compile(sources + ("programs/entry.S", "programs/init.c", "-I", "../env", + "-march=RV%dIMAF" % self.xlen, "-T", "targets/%s/link.lds" % (self.directory or self.name), "-nostartfiles", "-mcmodel=medany", |