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| author | Andrew Waterman <andrew@sifive.com> | 2016-12-12 22:51:27 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-12-12 23:18:06 -0800 |
| commit | 6855cddc0ff7bcc06e71aa24a0417fc0656e75fb (patch) | |
| tree | c300ead4374218dd4ae9f7bdcd111140551ef640 /debug/targets.py | |
| parent | f8910f9e782dbc1752a7d1b94c7b18bbc04178d3 (diff) | |
| download | riscv-tests-6855cddc0ff7bcc06e71aa24a0417fc0656e75fb.zip riscv-tests-6855cddc0ff7bcc06e71aa24a0417fc0656e75fb.tar.gz riscv-tests-6855cddc0ff7bcc06e71aa24a0417fc0656e75fb.tar.bz2 | |
Pass newly updated -march, -mabi options to gcc
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index 8c725c4..c431a67 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -39,9 +39,9 @@ class Target(object): prefix=binary_name + "_") binary_name = self.temporary_binary.name Target.temporary_files.append(self.temporary_binary) - march = "RV%dIMA" % self.xlen + march = "rv%dima" % self.xlen if self.use_fpu: - march += "FD" + march += "fd" testlib.compile(sources + ("programs/entry.S", "programs/init.c", "-I", "../env", |