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| author | Tim Newsome <tim@sifive.com> | 2017-10-05 12:48:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-05 12:48:40 -0700 |
| commit | cad03ed0e58693257176ebaf4cbb70484a44fd2e (patch) | |
| tree | cdd02426a6a429c2ac5ebf4d781b3519ea0c63f4 /debug/targets.py | |
| parent | 5eb2cf39af91f9d886e28175b729f02684c27df4 (diff) | |
| parent | 9091137e4a4797a91179ab73886697c7fe270da2 (diff) | |
| download | riscv-tests-interrupts.zip riscv-tests-interrupts.tar.gz riscv-tests-interrupts.tar.bz2 | |
Merge branch 'master' into interruptsinterrupts
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index d661d14..624eb71 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -34,6 +34,11 @@ class Hart(object): # Defaults to target-<index> name = None + # When reset, the PC must be at one of the values listed here. + # This is a list because on some boards the reset vector depends on + # jumpers. + reset_vectors = [] + def extensionSupported(self, letter): # target.misa is set by testlib.ExamineTarget if self.misa: @@ -91,6 +96,8 @@ class Target(object): self.openocd_config_path) for i, hart in enumerate(self.harts): hart.index = i + if not hasattr(hart, 'id'): + hart.id = i if not hart.name: hart.name = "%s-%d" % (self.name, i) # Default link script to <name>.lds |