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| author | Tim Newsome <tim@sifive.com> | 2016-09-29 11:38:54 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-09-29 11:38:54 -0700 |
| commit | ad4010d4b7147a6607c2fd30c7885ca6b464abbc (patch) | |
| tree | 4301b965a79f87fbaff17ae9d1918b2ceae0f0f6 /debug/programs | |
| parent | e7878124b84adf0bbd985ce6f39ab8dd203b5dbd (diff) | |
| download | riscv-tests-ad4010d4b7147a6607c2fd30c7885ca6b464abbc.zip riscv-tests-ad4010d4b7147a6607c2fd30c7885ca6b464abbc.tar.gz riscv-tests-ad4010d4b7147a6607c2fd30c7885ca6b464abbc.tar.bz2 | |
Clear triggers during entry.
If the last test leaves some triggers set they should be cleaned up.
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 80904cd..6dc694f 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -40,6 +40,15 @@ handle_reset: # initialize stack pointer la sp, stack_top + # Clear all hardware triggers + li t0, ~0 +1: + addi t0, t0, 1 + csrw CSR_TSELECT, t0 + csrw CSR_TDATA1, zero + csrr t1, CSR_TSELECT + beq t0, t1, 1b + # perform the rest of initialization in C j _init |