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author | Tim Newsome <tim@sifive.com> | 2018-02-09 08:54:59 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2018-02-09 08:54:59 -0800 |
commit | ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241 (patch) | |
tree | 2582ce2b92bb2f54fc67f24e7c5c12da32551044 /debug/programs/trigger.S | |
parent | 1637fcbfd1b25b7341767ab7caa7a8173f471a51 (diff) | |
download | riscv-tests-resume_from_trigger.zip riscv-tests-resume_from_trigger.tar.gz riscv-tests-resume_from_trigger.tar.bz2 |
Test resuming from a trigger.resume_from_trigger
Diffstat (limited to 'debug/programs/trigger.S')
-rw-r--r-- | debug/programs/trigger.S | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 3d502dc..13f0449 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -10,16 +10,6 @@ # define REGBYTES 4 #endif -#undef MCONTROL_TYPE -#undef MCONTROL_DMODE -#if __riscv_xlen == 64 -# define MCONTROL_TYPE (0xf<<(64-4)) -# define MCONTROL_DMODE (1<<(64-5)) -#else -# define MCONTROL_TYPE (0xf<<(32-4)) -# define MCONTROL_DMODE (1<<(32-5)) -#endif - .global main .section .text @@ -31,7 +21,10 @@ just_before_read_loop: li t2, 16 read_loop: lw t1, 0(a0) + addi t1, t1, 1 addi t0, t0, 1 +read_again: + lw t1, 0(a0) addi a0, a0, 4 blt t0, t2, read_loop |