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| author | Tim Newsome <tim@sifive.com> | 2022-07-01 10:19:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-01 10:19:23 -0700 |
| commit | 84524e9e0841b3a7c1baba13bed9c176126924df (patch) | |
| tree | a8598ddc2a67a843739fc57de127e10ef0e2c0ab /debug/openocd.py | |
| parent | fc38747b2dba58c7c80edd99e965c57a373cf294 (diff) | |
| download | riscv-tests-84524e9e0841b3a7c1baba13bed9c176126924df.zip riscv-tests-84524e9e0841b3a7c1baba13bed9c176126924df.tar.gz riscv-tests-84524e9e0841b3a7c1baba13bed9c176126924df.tar.bz2 | |
Complete this pass of pylint changes. (#401)
Diffstat (limited to 'debug/openocd.py')
| -rwxr-xr-x | debug/openocd.py | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/debug/openocd.py b/debug/openocd.py index 1b7c8fd..54b970f 100755 --- a/debug/openocd.py +++ b/debug/openocd.py @@ -25,7 +25,7 @@ class OpenOcdTest(testlib.BaseTest): def write_nops(self, count): for address in range(self.target.ram, self.target.ram + 4 * count, 4): # 0x13 is nop - self.cli.command("mww 0x%x 0x13" % address) + self.cli.command(f"mww 0x{address:x} 0x13") class RegTest(OpenOcdTest): def test(self): @@ -35,7 +35,7 @@ class RegTest(OpenOcdTest): assertIn("x18", regs) self.cli.command("reg x18 0x11782") - self.cli.command("step 0x%x" % self.target.ram) + self.cli.command(f"step 0x{self.target.ram:x}") assertEqual(self.cli.reg("x18"), 0x11782) @@ -43,7 +43,7 @@ class StepTest(OpenOcdTest): def test(self): self.write_nops(4) - self.cli.command("step 0x%x" % self.target.ram) + self.cli.command("step 0x{self.target.ram:x}") for i in range(4): pc = self.cli.reg("pc") assertEqual(pc, self.target.ram + 4 * (i+1)) @@ -53,16 +53,16 @@ class ResumeTest(OpenOcdTest): def test(self): self.write_nops(16) - self.cli.command("bp 0x%x 4" % (self.target.ram + 12)) - self.cli.command("bp 0x%x 4" % (self.target.ram + 24)) + self.cli.command(f"bp 0x{self.target.ram + 12:x} 4") + self.cli.command(f"bp 0x{self.target.ram + 24:x} 4") - self.cli.command("resume 0x%x" % self.target.ram) + self.cli.command(f"resume 0x{self.target.ram:x}") assertEqual(self.cli.reg("pc"), self.target.ram + 12) self.cli.command("resume") assertEqual(self.cli.reg("pc"), self.target.ram + 24) - self.cli.command("resume 0x%x" % self.target.ram) + self.cli.command(f"resume 0x{self.target.ram:x}") assertEqual(self.cli.reg("pc"), self.target.ram + 12) def main(): |