diff options
author | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
---|---|---|
committer | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
commit | 7d069666a5841e5e5b3ba1723c6af26925a35a9c (patch) | |
tree | c4c87bce99b8f2ce58a74e7250dbb1eeb778d78f /debug/gdbserver.py | |
parent | 3496243928e3dbd562dd84bcf9e6222221d423e5 (diff) | |
download | riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.zip riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.gz riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.bz2 |
Make HiFiveUnleashed tests clean.
HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.
Diffstat (limited to 'debug/gdbserver.py')
-rwxr-xr-x | debug/gdbserver.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 1e50272..314a775 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -253,7 +253,7 @@ class MemTest64(SimpleMemoryTest): class MemTestReadInvalid(SimpleMemoryTest): def test(self): - bad_address = self.hart.ram - 8 + bad_address = self.hart.bad_address good_address = self.hart.ram + 0x80 self.write_nop_program(2) |