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| author | Tim Newsome <tim@sifive.com> | 2016-07-18 18:32:45 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-19 11:24:25 -0700 |
| commit | 713f6a3089ac8b656d0a18874782e26d3039b22e (patch) | |
| tree | 895d79cd95e6988a74204af03baccd695e71674c /debug/Makefile | |
| parent | f254dce79dc5a278328699d65da2516545f5d31c (diff) | |
| download | riscv-tests-713f6a3089ac8b656d0a18874782e26d3039b22e.zip riscv-tests-713f6a3089ac8b656d0a18874782e26d3039b22e.tar.gz riscv-tests-713f6a3089ac8b656d0a18874782e26d3039b22e.tar.bz2 | |
Be verbose, since output is going to a log file.
Diffstat (limited to 'debug/Makefile')
| -rw-r--r-- | debug/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/Makefile b/debug/Makefile index a138f25..62d7875 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -3,10 +3,10 @@ RISCV_SIM ?= spike all: spike32.log spike64.log spike32.log: - ./gdbserver.py --isolate --spike32 --cmd $(RISCV_SIM) > $@ 2>&1 + ./gdbserver.py --isolate --spike32 --cmd $(RISCV_SIM) -- -v > $@ 2>&1 spike64.log: - ./gdbserver.py --isolate --spike --cmd $(RISCV_SIM) > $@ 2>&1 + ./gdbserver.py --isolate --spike --cmd $(RISCV_SIM) -- -v > $@ 2>&1 clean: rm -f *.log |