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| author | Christopher Celio <celio@eecs.berkeley.edu> | 2014-09-10 14:17:01 -0700 |
|---|---|---|
| committer | Christopher Celio <celio@eecs.berkeley.edu> | 2014-09-10 14:17:01 -0700 |
| commit | dbde501592ce20c536cbc97e99d03f54f3e30294 (patch) | |
| tree | 4c66ef6d1563409724f704e0e3905b0e40e02e0c /benchmarks | |
| parent | 3af71c779ae5f34c16c1133b972b99ee9c2338b5 (diff) | |
| download | riscv-tests-dbde501592ce20c536cbc97e99d03f54f3e30294.zip riscv-tests-dbde501592ce20c536cbc97e99d03f54f3e30294.tar.gz riscv-tests-dbde501592ce20c536cbc97e99d03f54f3e30294.tar.bz2 | |
Enable interrupts in bmarks
Diffstat (limited to 'benchmarks')
| -rw-r--r-- | benchmarks/common/crt.S | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 82cad93..e35608e 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -44,21 +44,20 @@ _start: li x30,0 li x31,0 + # initialize status, enable fp, accelerator, interrupts + li a0, SR_S | SR_PEI | SR_EF | SR_EA + csrw status, a0 + #ifdef __riscv64 li a0, SR_U64 | SR_S64 csrs status, a0 #endif - csrc status, SR_PS - - # enable fp and accelerator - li a0, SR_EF | SR_EA - csrs status, a0 csrr t0, status and t1, t0, SR_EA sw t1, have_vec, t2 - ## if that didn't stick, we don't have an FPU, so don't initialize it + ## if that didn't stick, we don't have a FPU, so don't initialize it and t1, t0, SR_EF beqz t1, 1f |