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author | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2014-04-03 16:47:43 -0700 |
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committer | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2014-04-03 16:47:43 -0700 |
commit | b961c327162755de390b9175c792ffeb309f82a6 (patch) | |
tree | f63162dc51a5697ee5ff6b2b4ad2752603312335 /benchmarks/common/syscalls.c | |
parent | 542e4095a2e5c72546a4922399a9f7e056eaa022 (diff) | |
download | riscv-tests-b961c327162755de390b9175c792ffeb309f82a6.zip riscv-tests-b961c327162755de390b9175c792ffeb309f82a6.tar.gz riscv-tests-b961c327162755de390b9175c792ffeb309f82a6.tar.bz2 |
setStats in benchmarks now should set and unset the stats register. Also, removed legacy SET_STATS macro.
Diffstat (limited to 'benchmarks/common/syscalls.c')
-rw-r--r-- | benchmarks/common/syscalls.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c index d506536..fbbb880 100644 --- a/benchmarks/common/syscalls.c +++ b/benchmarks/common/syscalls.c @@ -34,6 +34,13 @@ static long counters[NUM_COUNTERS]; static char* counter_names[NUM_COUNTERS]; static int handle_stats(int enable) { + //use csrs to set stats register + if(enable) { + asm volatile (R"( + addi v0, x0, 1 + csrrs v0, stats, v0 + )" : : : "v0"); + } int i = 0; #define READ_CTR(name) do { \ while (i >= NUM_COUNTERS) ; \ @@ -47,6 +54,12 @@ static int handle_stats(int enable) READ_CTR(uarch8); READ_CTR(uarch9); READ_CTR(uarch10); READ_CTR(uarch11); READ_CTR(uarch12); READ_CTR(uarch13); READ_CTR(uarch14); READ_CTR(uarch15); #undef READ_CTR + if(!enable) { + asm volatile (R"( + addi v0, x0, 1 + csrrc v0, stats, v0 + )" : : : "v0"); + } return 0; } @@ -59,7 +72,7 @@ static void tohost_exit(int code) long handle_trap(long cause, long epc, long regs[32]) { int csr_insn; - asm volatile ("lw %0, 1f; j 2f; 1: csrr v0, uarch0; 2:" : "=r"(csr_insn)); + asm volatile ("lw %0, 1f; j 2f; 1: csrr v0, stats; 2:" : "=r"(csr_insn)); long sys_ret = 0; if (cause == CAUSE_ILLEGAL_INSTRUCTION && |