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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:03:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:03:03 -0700 |
| commit | cacfb9ab5f4cb3359ee1ed769e7f1989409c2c1d (patch) | |
| tree | 132fd50818b911640914a772d4e9de146b1d167d | |
| parent | 959218673db6737d65014f93208b9240c85eb8a6 (diff) | |
| download | riscv-tests-cacfb9ab5f4cb3359ee1ed769e7f1989409c2c1d.zip riscv-tests-cacfb9ab5f4cb3359ee1ed769e7f1989409c2c1d.tar.gz riscv-tests-cacfb9ab5f4cb3359ee1ed769e7f1989409c2c1d.tar.bz2 | |
Add HW breakpoint test
| m--------- | env | 10 | ||||
| -rw-r--r-- | isa/rv64mi/Makefrag | 1 | ||||
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 97 |
3 files changed, 103 insertions, 5 deletions
diff --git a/env b/env -Subproject e0d1ea452c2a40ca47ec720e7da8c31daa31730 +Subproject 2feb57e3bfb9814b2b21b0dfdfbe2c7ef26db5f diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag index 01f75c2..4ae8733 100644 --- a/isa/rv64mi/Makefrag +++ b/isa/rv64mi/Makefrag @@ -3,6 +3,7 @@ #----------------------------------------------------------------------- rv64mi_sc_tests = \ + breakpoint \ dirty \ csr \ mcsr \ diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S new file mode 100644 index 0000000..39d058b --- /dev/null +++ b/isa/rv64mi/breakpoint.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# breakpoint.S +#----------------------------------------------------------------------------- +# +# Test breakpoints, if they are implemented. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Set up breakpoint to trap on M-mode fetches. + li TESTNUM, 2 + csrw tdrselect, x0 + li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_X + csrw tdrdata1, t0 + # Skip if breakpoint type is unsupported. + csrr t1, tdrdata1 + bne t0, t1, 2f + la t0, 1f + csrw tdrdata2, t0 +1: + # Trap handler should skip this instruction. + j fail + + # Make sure reads don't trap. + li TESTNUM, 3 + lw t0, (t0) + +2: + # Set up breakpoint to trap on M-mode reads. + li TESTNUM, 4 + li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_R + csrw tdrdata1, t0 + # Skip if breakpoint type is unsupported. + csrr t1, tdrdata1 + bne t0, t1, 2f + la t0, write_data + csrw tdrdata2, t0 + + # Trap handler should skip this instruction. + lw t0, (t0) + beqz t0, fail + + # Make sure writes don't trap. + li TESTNUM, 5 + sw x0, (t0) + +2: + # Set up breakpoint to trap on M-mode stores. + li TESTNUM, 6 + li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_W + csrw tdrdata1, t0 + # Skip if breakpoint type is unsupported. + csrr t1, tdrdata1 + bne t0, t1, 2f + + # Trap handler should skip this instruction. + la t0, write_data + sw t0, (t0) + + # Make sure store didn't succeed. + li TESTNUM, 7 + lw t0, (t0) + bnez t0, fail + +2: + TEST_PASSFAIL + +mtvec_handler: + # Only even-numbered tests should trap. + andi a0, TESTNUM, 1 + bnez a0, fail + + li a0, CAUSE_BREAKPOINT + csrr a1, mcause + bne a0, a1, fail + + csrr a0, mepc + addi a0, a0, 4 + csrw mepc, a0 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +write_data: .word 0 + +RVTEST_DATA_END |