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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-11-22 10:29:30 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-11-22 10:29:30 -0800 |
| commit | bebcfb0747bb31b0e2f4834f61afcf089135d3cc (patch) | |
| tree | 7e051c28cc444b8c207e1886e2193cc3d4ed5d7a | |
| parent | d15d7a7bdb316d8b0008654b5d965ba4f1c2c7da (diff) | |
| download | riscv-tests-bebcfb0747bb31b0e2f4834f61afcf089135d3cc.zip riscv-tests-bebcfb0747bb31b0e2f4834f61afcf089135d3cc.tar.gz riscv-tests-bebcfb0747bb31b0e2f4834f61afcf089135d3cc.tar.bz2 | |
relax rv32si timer test a bit
| -rw-r--r-- | isa/rv32si/timer.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S index d46c2fd..4048875 100644 --- a/isa/rv32si/timer.S +++ b/isa/rv32si/timer.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN csrsi status, 4 # enable interrupts li TESTNUM, 2 - li a0,1000 + li a0,10000 loop: div x0, x0, x0 addi a0, a0, -1 @@ -33,6 +33,7 @@ loop: TEST_PASSFAIL evec: + li TESTNUM, 3 li t1, 0x80000000|IRQ_TIMER csrr t0, cause bne t0, t1, fail |