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| author | Tim Newsome <tim@sifive.com> | 2016-06-21 13:56:32 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-18 18:51:54 -0700 |
| commit | 6aa5ac06c704ea822bd1150e5c2d8900ce380807 (patch) | |
| tree | 70bc356ffb342f07e54b68bf8911475b943e12e6 | |
| parent | 72822ba60b710dc2ce0c9cffbc990d99e93490c1 (diff) | |
| download | riscv-tests-6aa5ac06c704ea822bd1150e5c2d8900ce380807.zip riscv-tests-6aa5ac06c704ea822bd1150e5c2d8900ce380807.tar.gz riscv-tests-6aa5ac06c704ea822bd1150e5c2d8900ce380807.tar.bz2 | |
Remove hardware breakpoints so future tests work.
| -rwxr-xr-x | debug/gdbserver.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index deb3d57..030b6a1 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -241,6 +241,9 @@ class DebugTest(DeleteServer): output = self.gdb.c() self.assertIn("Cannot insert hardware breakpoint", output) + # Clean up, otherwise the hardware breakpoints stay set and future + # tests may fail. + self.gdb.command("D") def test_registers(self): # Get to a point in the code where some registers have actually been |