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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-14 02:08:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-14 02:08:03 -0700 |
| commit | 62f8f78b5fc18e2f89e4b6429352ca4c980908c7 (patch) | |
| tree | 7f13900c6bd19bd2e53d1e8111a1b629a8c2affe | |
| parent | cbb938f57d7f609ee6bb2e8b2151a2b041b700aa (diff) | |
| download | riscv-tests-62f8f78b5fc18e2f89e4b6429352ca4c980908c7.zip riscv-tests-62f8f78b5fc18e2f89e4b6429352ca4c980908c7.tar.gz riscv-tests-62f8f78b5fc18e2f89e4b6429352ca4c980908c7.tar.bz2 | |
Add PTE dirty bit test
| m--------- | env | 10 | ||||
| -rw-r--r-- | isa/rv64si/Makefrag | 1 | ||||
| -rw-r--r-- | isa/rv64si/dirty.S | 84 |
3 files changed, 90 insertions, 5 deletions
diff --git a/env b/env -Subproject bd2090129b328fa9803275df0e52459d645e8ce +Subproject 4ea6feac5fe663fe82de53632883ced6205f57f diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index c5a5d95..87982c6 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -5,6 +5,7 @@ rv64si_sc_tests = \ csr \ timer \ + dirty \ rv64si_mc_tests = \ ipi \ diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S new file mode 100644 index 0000000..87a619a --- /dev/null +++ b/isa/rv64si/dirty.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# dirty.S +#----------------------------------------------------------------------------- +# +# Test VM referenced and dirty bits. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Turn on VM with superpage identity mapping + la a1, handler + csrw stvec, a1 + la a1, page_table_1 + csrw sptbr, a1 + sfence.vm + li a1, (MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43 + csrs mstatus, a1 + la a1, 1f + csrw mepc, a1 + mret +1: + + # Try a faulting store to make sure dirty bit is not set + li TESTNUM, 2 + li t0, 1 + sd t0, dummy, t1 + + # Load new page table + li TESTNUM, 3 + la t0, page_table_2 + csrw sptbr, t0 + sfence.vm + + # Try a non-faulting store to make sure dirty bit is set + sd t0, dummy, t1 + + # Make sure R and D bits are set + lw t0, page_table_2 + li t1, PTE_R | PTE_D + and t0, t0, t1 + bne t0, t1, die + + RVTEST_PASS + + TEST_PASSFAIL + +handler: + csrr t0, scause + li t1, 2 + bne TESTNUM, t1, 1f + # Make sure R bit is set + lw t0, page_table_1 + li t1, PTE_R + and t0, t0, t1 + bne t0, t1, die + + # Make sure D bit is clear + lw t0, page_table_1 + li t1, PTE_D + and t0, t0, t1 + beq t0, t1, die + + csrr t0, sepc + add t0, t0, 4 + csrw sepc, t0 + sret + +die: + RVTEST_FAIL + +.data +.align 13 +page_table_1: .dword PTE_V | PTE_SX | PTE_SR +dummy: .dword 0 +.align 13 +page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW + +RVTEST_CODE_END |