split out S-mode tests and M-mode tests

43 files changed, 283 insertions, 102 deletions

diff --git a/env b/env
-Subproject 104ce71726ee9ae95f920b42462afb30baeeb36
+Subproject fe2bd085aaef12c043672b2bb07fc1daab9ce59
diff --git a/isa/Makefile b/isa/Makefile
index 4c84815..229a509 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -9,8 +9,10 @@ include $(isa_src_dir)/rv64uf/Makefrag
 include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
 include $(isa_src_dir)/rv64sv/Makefrag
+include $(isa_src_dir)/rv64mi/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
 include $(isa_src_dir)/rv32si/Makefrag
+include $(isa_src_dir)/rv32mi/Makefrag
 
 default: all
 
@@ -81,11 +83,13 @@ endef
 
 $(eval $(call compile_template,rv32ui,-m32))
 $(eval $(call compile_template,rv32si,-m32))
+$(eval $(call compile_template,rv32mi,-m32))
 $(eval $(call compile_template,rv64ui))
 $(eval $(call compile_template,rv64uf))
 $(eval $(call compile_template,rv64uv))
 $(eval $(call compile_template,rv64si))
 $(eval $(call compile_template,rv64sv))
+$(eval $(call compile_template,rv64mi))
 
 tests_dump = $(addsuffix .dump, $(tests))
 tests_hex = $(addsuffix .hex, $(tests))
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
new file mode 100644
index 0000000..e6ab8c8
--- /dev/null
+++ b/isa/rv32mi/Makefrag
@@ -0,0 +1,18 @@
+#=======================================================================
+# Makefrag for rv32mi tests
+#-----------------------------------------------------------------------
+
+rv32mi_sc_tests = \
+	csr \
+	illegal \
+	ma_fetch \
+	ma_addr \
+	scall \
+	sbreak \
+	timer \
+
+rv32mi_mc_tests = \
+	ipi \
+
+rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
+rv32mi_pm_tests = $(addprefix rv32mi-pm-, $(rv32mi_mc_tests))
diff --git a/isa/rv32mi/csr.S b/isa/rv32mi/csr.S
new file mode 100644
index 0000000..6361f86
--- /dev/null
+++ b/isa/rv32mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"
diff --git a/isa/rv32mi/illegal.S b/isa/rv32mi/illegal.S
new file mode 100644
index 0000000..c357ed7
--- /dev/null
+++ b/isa/rv32mi/illegal.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/illegal.S"
diff --git a/isa/rv32mi/ipi.S b/isa/rv32mi/ipi.S
new file mode 100644
index 0000000..c39fc29
--- /dev/null
+++ b/isa/rv32mi/ipi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/ipi.S"
diff --git a/isa/rv32mi/ma_addr.S b/isa/rv32mi/ma_addr.S
new file mode 100644
index 0000000..df5099a
--- /dev/null
+++ b/isa/rv32mi/ma_addr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_addr.S"
diff --git a/isa/rv32mi/ma_fetch.S b/isa/rv32mi/ma_fetch.S
new file mode 100644
index 0000000..ec0e0f6
--- /dev/null
+++ b/isa/rv32mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"
diff --git a/isa/rv32mi/sbreak.S b/isa/rv32mi/sbreak.S
new file mode 100644
index 0000000..c1b127d
--- /dev/null
+++ b/isa/rv32mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"
diff --git a/isa/rv32mi/scall.S b/isa/rv32mi/scall.S
new file mode 100644
index 0000000..e5b3153
--- /dev/null
+++ b/isa/rv32mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"
diff --git a/isa/rv32mi/timer.S b/isa/rv32mi/timer.S
new file mode 100644
index 0000000..58dac99
--- /dev/null
+++ b/isa/rv32mi/timer.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/timer.S"
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 70cea70..e03819f 100644
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -12,10 +12,4 @@ rv32si_sc_tests = \
 	ma_addr \
 	timer \
 
-rv32si_mc_tests = \
-	ipi \
-
 rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
-rv32si_pm_tests = $(addprefix rv32si-pm-, $(rv32si_mc_tests))
-
-spike_tests += $(rv32si_p_tests) $(rv32si_pm_tests)
diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S
deleted file mode 100644
index 7e11423..0000000
--- a/isa/rv32si/ipi.S
+++ /dev/null
@@ -1,7 +0,0 @@
-# See LICENSE for license details.
-
-#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32S
-
-#include "../rv64si/ipi.S"
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
new file mode 100644
index 0000000..db40dc1
--- /dev/null
+++ b/isa/rv64mi/Makefrag
@@ -0,0 +1,21 @@
+#=======================================================================
+# Makefrag for rv64mi tests
+#-----------------------------------------------------------------------
+
+rv64mi_sc_tests = \
+	dirty \
+	csr \
+	illegal \
+	ma_fetch \
+	ma_addr \
+	scall \
+	sbreak \
+	timer \
+
+rv64mi_mc_tests = \
+	ipi \
+
+rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
+rv64mi_pm_tests = $(addprefix rv64mi-pm-, $(rv64mi_mc_tests))
+
+spike_tests += $(rv64mi_p_tests) $(rv64mi_pm_tests)
diff --git a/isa/rv64mi/csr.S b/isa/rv64mi/csr.S
new file mode 100644
index 0000000..77e7619
--- /dev/null
+++ b/isa/rv64mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"
diff --git a/isa/rv64si/dirty.S b/isa/rv64mi/dirty.S
index e5f4db6..f343cf9 100644
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -14,8 +14,6 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # Turn on VM with superpage identity mapping
-  la a1, handler
-  csrw stvec, a1
   la a1, page_table_1
   csrw sptbr, a1
   sfence.vm
@@ -50,7 +48,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-handler:
+stvec_handler:
   csrr t0, scause
   li t1, 2
   bne TESTNUM, t1, 1f
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
new file mode 100644
index 0000000..c5ccffd
--- /dev/null
+++ b/isa/rv64mi/illegal.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/illegal.S"
diff --git a/isa/rv64si/ipi.S b/isa/rv64mi/ipi.S
index e45c663..326476d 100644
--- a/isa/rv64si/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -37,7 +37,7 @@ RVTEST_CODE_BEGIN
   csrw send_ipi, a0
   1: j 1b
 
-mtvec:
+mtvec_handler:
   csrr a0, hartid
   bnez a0, 2f
   RVTEST_PASS
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
new file mode 100644
index 0000000..0448736
--- /dev/null
+++ b/isa/rv64mi/ma_addr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_addr.S"
diff --git a/isa/rv64mi/ma_fetch.S b/isa/rv64mi/ma_fetch.S
new file mode 100644
index 0000000..cfcb90c
--- /dev/null
+++ b/isa/rv64mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"
diff --git a/isa/rv64mi/sbreak.S b/isa/rv64mi/sbreak.S
new file mode 100644
index 0000000..f36a9f8
--- /dev/null
+++ b/isa/rv64mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"
diff --git a/isa/rv64mi/scall.S b/isa/rv64mi/scall.S
new file mode 100644
index 0000000..22e9eb5
--- /dev/null
+++ b/isa/rv64mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"
diff --git a/isa/rv64mi/timer.S b/isa/rv64mi/timer.S
new file mode 100644
index 0000000..f491530
--- /dev/null
+++ b/isa/rv64mi/timer.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/timer.S"
diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index 802fc55..f19d840 100644
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -10,12 +10,7 @@ rv64si_sc_tests = \
 	scall \
 	sbreak \
 	timer \
-	dirty \
-
-rv64si_mc_tests = \
-	ipi \
 
 rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
-rv64si_pm_tests = $(addprefix rv64si-pm-, $(rv64si_mc_tests))
 
-spike_tests += $(rv64si_p_tests) $(rv64si_pm_tests)
+spike_tests += $(rv64si_p_tests)
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index edaaeb3..5d4b309 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -13,9 +13,16 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  # Set up stvec in case we trap.
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_PS
+  #define SSTATUS_PS MSTATUS_PRV1
+#endif
+
   csrwi scycle, 0
 
   csrwi sscratch, 3
@@ -31,7 +38,7 @@ RVTEST_CODE_BEGIN
   # Make sure writing the cycle counter causes an exception.
   TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
 
-  # Enter user mode
+  # jump to user land
   li t0, SSTATUS_PS
   csrc sstatus, t0
   la t0, 1f
@@ -51,7 +58,7 @@ RVTEST_CODE_BEGIN
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   # Trapping on tests 10, 11, and 13 is usually good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 9
@@ -65,7 +72,7 @@ stvec:
   j fail
 
 privileged:
-  # Make sure CAUSE indicates a lack of privilege.
+  # Make sure scause indicates a lack of privilege.
   csrr t0, scause
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   bne t0, t1, fail
@@ -76,7 +83,7 @@ privileged:
   sret
 
 syscall:
-  # Make sure CAUSE indicates a syscall.
+  # Make sure scause indicates a syscall.
   csrr t0, scause
   li t1, CAUSE_ECALL
   bne t0, t1, fail
diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S
index b068118..43068b4 100644
--- a/isa/rv64si/illegal.S
+++ b/isa/rv64si/illegal.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   .word 0
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   csrr t0, scause
   bne t0, t1, fail
diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S
index 19abe96..525e028 100644
--- a/isa/rv64si/ma_addr.S
+++ b/isa/rv64si/ma_addr.S
@@ -13,10 +13,18 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la s0, stvec_load
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
+
+  la s0, stvec_handler
 
-  la t0, stvec_load
-  csrw stvec, t0
+  # indicate it's a load test
+  li s1, 0
 
 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
   li TESTNUM, testnum; \
@@ -43,8 +51,8 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(16, ld, s0, 7)
 #endif
 
-  la t0, stvec_store
-  csrw stvec, t0
+  # indicate it's a store test
+  li s1, 1
 
   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
@@ -64,7 +72,10 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 3
-stvec_load:
+stvec_handler:
+  bnez s1, test_store
+
+test_load:
   li t1, CAUSE_MISALIGNED_LOAD
   csrr t0, scause
   bne t0, t1, fail
@@ -73,7 +84,7 @@ stvec_load:
   csrw sepc, t0
   sret
 
-stvec_store:
+test_store:
   li t1, CAUSE_MISALIGNED_STORE
   csrr t0, scause
   bne t0, t1, fail
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index ae8377d..272a9eb 100644
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
 #ifndef __rvc
   li TESTNUM, 2
@@ -47,7 +52,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   # tests 2 and 4 should trap
   li a0, 2
   beq TESTNUM, a0, 1f
diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index dbdf7ae..bf38434 100644
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   sbreak
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
   bne t0, t1, fail
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index aa543e9..e1c13b6 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   scall
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_ECALL
   csrr t0, scause
   bne t0, t1, fail
diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S
index 584ced7..c78d922 100644
--- a/isa/rv64si/timer.S
+++ b/isa/rv64si/timer.S
@@ -1,10 +1,10 @@
 # See LICENSE for license details.
 
 #*****************************************************************************
-# ipi.S
+# timer.S
 #-----------------------------------------------------------------------------
 #
-# Test interprocessor interrupts.
+# Test timer interrupts.
 #
 
 #include "riscv_test.h"
@@ -13,16 +13,35 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  # clear pending IPIs then enable interrupts
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_PS
+  #define SSTATUS_PS MSTATUS_PRV1
+  #undef SSTATUS_IE
+  #define SSTATUS_IE MSTATUS_IE
+  #undef SSTATUS_TIE
+  #define SSTATUS_TIE MSTATUS_STIE
+#endif
+
   li s8, 0         # number of taken timer interrupts
   li s9, 10        # how many interrupts to run for
-  la a0, handler
-  csrw stvec, a0
   csrw stimecmp, 1
   csrw stime, 0
   li a0, SSTATUS_IE | SSTATUS_TIE
   csrs sstatus, a0
 
+  # jump to user land
+  li t0, SSTATUS_PS
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+  1:
+
   # advance an LFSR 1000 times
   li s0, 1023
   li s4, 0
@@ -36,8 +55,6 @@ RVTEST_CODE_BEGIN
   add s4, s4, 1
   bltu s8, s9, 1b
 
-  csrc sstatus, SSTATUS_IE
-
   # make sure the LFSR was computed correctly
   li s1, 1023
   remu s4, s4, s1
@@ -52,7 +69,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-handler:
+stvec_handler:
   li TESTNUM, 3
   csrr t0, scause
   bgez t0, fail
@@ -66,7 +83,13 @@ handler:
   csrw stimecmp, t0
 
   add s8, s8, 1
+  bltu s8, s9, stvec_return
+
+  li t0, SSTATUS_PS
+  csrs sstatus, t0
+  csrc sstatus, SSTATUS_IE
 
+stvec_return:
   sret
 
 .data
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index 03227eb..be114cc 100644
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a0,33
   slli a0,a0,6
   vsetcfg a0
@@ -24,7 +21,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index dc4d3a4..51cc84a 100644
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a0,33
   vsetcfg a0
 
@@ -23,7 +20,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index b7dfc28..7e653d1 100644
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   .word 0xff00002b
 
   vsetcfg 32,0
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index a2090ac..30403ba 100644
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -21,6 +21,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index e216413..080cd2f 100644
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,7 +35,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 24745dc..e74b614 100644
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -23,6 +23,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 79b21b1..5ea6ee6 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -34,7 +31,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 9bd3cd8..47df11b 100644
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -36,7 +33,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 85882b8..2cdc2d4 100644
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -35,7 +32,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 35cb828..e113f99 100644
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,7 +35,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index d7c96b3..a257942 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -28,7 +25,7 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 65c5288..e59d361 100644
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a3, SSTATUS_PS
   csrc sstatus, a3
   la t0, 1f
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2