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| author | Tim Newsome <tim@sifive.com> | 2018-02-19 13:31:40 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-02-28 12:37:40 -0800 |
| commit | 400ad944db31fe736c166967567cc8a63d300e6c (patch) | |
| tree | c21a01a4c99b8f11f5f7e384496828d85e14e16c | |
| parent | ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241 (diff) | |
| download | riscv-tests-no_progbuf.zip riscv-tests-no_progbuf.tar.gz riscv-tests-no_progbuf.tar.bz2 | |
Test debugging with/without a program bufferno_progbuf
| -rw-r--r-- | debug/Makefile | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 2 | ||||
| -rw-r--r-- | debug/testlib.py | 7 |
5 files changed, 10 insertions, 5 deletions
diff --git a/debug/Makefile b/debug/Makefile index 8e1c81b..48be07c 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -4,7 +4,7 @@ XLEN ?= 64 src_dir ?= . GDBSERVER_PY = $(src_dir)/gdbserver.py -default: spike$(XLEN)-2 +default: spike$(XLEN) spike$(XLEN)-2 all-tests: spike32 spike32-2 spike32-2-rtos spike64 spike64-2 spike64-2-rtos diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index a7b9a1c..79105d5 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self) + return testlib.Spike(self, progbufsize=0) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index f57f816..89d3c2a 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self, isa="RV32IMAFC") + return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 2aa1dd0..d5802b5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -16,4 +16,4 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only - return testlib.Spike(self, isa="RV64IMAFC") + return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0) diff --git a/debug/testlib.py b/debug/testlib.py index 3aaa542..5c40a5d 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -57,11 +57,12 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin class Spike(object): def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True, - isa=None): + isa=None, progbufsize=None): """Launch spike. Return tuple of its process and the port it's running on.""" self.process = None self.isa = isa + self.progbufsize = progbufsize if target.harts: harts = target.harts @@ -118,6 +119,10 @@ class Spike(object): cmd += ["--isa", isa] + if not self.progbufsize is None: + cmd += ["--progsize", str(self.progbufsize)] + cmd += ["--debug-sba", "32"] + assert len(set(t.ram for t in harts)) == 1, \ "All spike harts must have the same RAM layout" assert len(set(t.ram_size for t in harts)) == 1, \ |