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| author | Samuel Obuch <samuel.obuch17@gmail.com> | 2020-10-08 20:52:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-08 11:52:47 -0700 |
| commit | ce7ec3b6b113f81f2afd362b4ea330d37e3b3df1 (patch) | |
| tree | 0b9c78fd643d9133b15350e53e0ad9f93826f8a7 | |
| parent | f1d5f44abc6fd7fc7b9edf65d61cb2154900157f (diff) | |
| download | riscv-tests-ce7ec3b6b113f81f2afd362b4ea330d37e3b3df1.zip riscv-tests-ce7ec3b6b113f81f2afd362b4ea330d37e3b3df1.tar.gz riscv-tests-ce7ec3b6b113f81f2afd362b4ea330d37e3b3df1.tar.bz2 | |
Expose registers on all harts in openocd cfgs (#297)
| -rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 7 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index 94bac00..c378a45 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -19,8 +19,11 @@ gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 +foreach t [target names] { + targets $t + riscv expose_csrs 2288 + riscv expose_custom 1,12345-12348 +} init diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 0eadb89..640fba9 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -18,8 +18,11 @@ gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 +foreach t [target names] { + targets $t + riscv expose_csrs 2288 + riscv expose_custom 1,12345-12348 +} init |