Add support to run all tests against HiFive Unleashed. (#212)

* Parse inf/nan floats.

* Enable mstatus.fs in SimpleF18Test

Also accept "unable to fetch" message when FPRs aren't supported.

* Add config files for HiFive Unleashed.

* Add configs to flash HiFive Unleashed.

All tests pass.

7 files changed, 191 insertions, 3 deletions

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index b0dc6bc..84d3f1d 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -119,6 +119,8 @@ class SimpleT1Test(SimpleRegisterTest):
 class SimpleF18Test(SimpleRegisterTest):
     def check_reg(self, name, alias):
         if self.hart.extensionSupported('F'):
+            mstatus_fs = 0x00006000
+            self.gdb.p("$mstatus=$mstatus|0x%x" % mstatus_fs)
             self.gdb.stepi()
             a = random.random()
             b = random.random()
@@ -140,9 +142,9 @@ class SimpleF18Test(SimpleRegisterTest):
                 assertEqual(size, 4)
         else:
             output = self.gdb.p_raw("$" + name)
-            assertEqual(output, "void")
+            assertRegexpMatches(output, r"void|Could not fetch register.*")
             output = self.gdb.p_raw("$" + alias)
-            assertEqual(output, "void")
+            assertRegexpMatches(output, r"void|Could not fetch register.*")
 
     def test(self):
         self.check_reg("f18", "fs2")
diff --git a/debug/targets/SiFive/HiFiveUnleashed-flash.lds b/debug/targets/SiFive/HiFiveUnleashed-flash.lds
new file mode 100644
index 0000000..b8bf92a
--- /dev/null
+++ b/debug/targets/SiFive/HiFiveUnleashed-flash.lds
@@ -0,0 +1,41 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x20000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+  _text_end = .;
+
+  . = 0x80000000;
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ASSERT(_text_end < 0x20100000, "program is too large")
+ASSERT(_end < 0x80100000, "program is too large")
diff --git a/debug/targets/SiFive/HiFiveUnleashed-flash.py b/debug/targets/SiFive/HiFiveUnleashed-flash.py
new file mode 100644
index 0000000..cb2741e
--- /dev/null
+++ b/debug/targets/SiFive/HiFiveUnleashed-flash.py
@@ -0,0 +1,22 @@
+import targets
+
+class E51(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "HiFiveUnleashed-flash.lds"
+    reset_vectors = [0x1004]
+
+class U54(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "HiFiveUnleashed-flash.lds"
+    reset_vectors = [0x1004]
+
+class HiFiveUnleashedFlash(targets.Target):
+    support_hasel = False
+    harts = [E51(), U54(), U54(), U54(), U54()]
+    openocd_config_path = "HiFiveUnleashed.cfg"
diff --git a/debug/targets/SiFive/HiFiveUnleashed.cfg b/debug/targets/SiFive/HiFiveUnleashed.cfg
new file mode 100644
index 0000000..d883914
--- /dev/null
+++ b/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -0,0 +1,64 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+set _TARGETNAME_0 $_CHIPNAME.cpu0
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+set _TARGETNAME_2 $_CHIPNAME.cpu2
+set _TARGETNAME_3 $_CHIPNAME.cpu3
+set _TARGETNAME_4 $_CHIPNAME.cpu4
+target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
+target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
+target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
+target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4
+target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+
+#set _TARGETNAME_0 $_CHIPNAME.cpu
+#target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0 -rtos riscv
+
+$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
+#>>>
+reset_config trst_and_srst
+adapter_nsrst_assert_width 100
+#<<<
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10040000
+init
+
+# Clear reset on these events, because that messes with memory which we don't
+# want in these tests. We want gdb be able to "download" to flash as well as
+# RAM, and then simply execute the program.
+# This must happen after init, where blank events get overwritten with reset.
+set targets [target names]
+foreach t $targets {
+    $t configure -event gdb-flash-erase-start ""
+    $t configure -event gdb-flash-write-end ""
+}
+
+reset
+
+halt
+
+# Uncomment this if you want to be able to clobber your SPI Flash, which
+# probably you don't since you can do it through Linux
+#flash protect 0 0 last off
+
+echo "Ready for Remote Connections"
diff --git a/debug/targets/SiFive/HiFiveUnleashed.lds b/debug/targets/SiFive/HiFiveUnleashed.lds
new file mode 100644
index 0000000..9298153
--- /dev/null
+++ b/debug/targets/SiFive/HiFiveUnleashed.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ASSERT(_end < 0x80100000, "program is too large")
diff --git a/debug/targets/SiFive/HiFiveUnleashed.py b/debug/targets/SiFive/HiFiveUnleashed.py
new file mode 100644
index 0000000..dd92a53
--- /dev/null
+++ b/debug/targets/SiFive/HiFiveUnleashed.py
@@ -0,0 +1,19 @@
+import targets
+
+class E51(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    reset_vectors = [0x1004]
+
+class U54(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    reset_vectors = [0x1004]
+
+class HiFiveUnleashed(targets.Target):
+    support_hasel = False
+    harts = [E51(), U54(), U54(), U54(), U54()]
diff --git a/debug/testlib.py b/debug/testlib.py
index 92e6ab6..60cb897 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -392,8 +392,10 @@ def parse_rhs(text):
     elif ' = ' in text:
         lhs, rhs = text.split(' = ', 1)
         return {lhs: parse_rhs(rhs)}
-    elif re.match(r"-?\d+\.\d+(e-?\d+)?", text):
+    elif re.match(r"-?(\d+\.\d+(e-?\d+)?|inf)", text):
         return float(text)
+    elif re.match(r"-nan\(0x[a-f0-9]+\)", text):
+        return float("nan")
     else:
         return int(text, 0)