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authorNils Asmussen <nils@os.inf.tu-dresden.de>2020-02-21 21:24:50 +0100
committerGitHub <noreply@github.com>2020-02-21 12:24:50 -0800
commit6fa1896b2a3f581359f0b6a952542f814e30602c (patch)
treef402c8b284f50732aff69883d3fef750be14df20
parentb6f7299a2df870b14cd437c555e048dfe49a2ba9 (diff)
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scall: make the intention of the test in machine mode more clear (#246)
-rw-r--r--isa/rv64si/scall.S7
1 files changed, 6 insertions, 1 deletions
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 82f202a..77718f2 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -19,7 +19,6 @@ RVTEST_CODE_BEGIN
#define scause mcause
#define sepc mepc
#define sret mret
- #define stvec_handler mtvec_handler
#undef SSTATUS_SPP
#define SSTATUS_SPP MSTATUS_MPP
#endif
@@ -57,6 +56,11 @@ do_scall:
TEST_PASSFAIL
+# make the linker not find the symbol stvec_handler when running in machine
+# mode. env/p/riscv_test.h sets stvec to the address of that symbol in case it
+# is non-zero. thus, effectively, we don't register a handler for scalls, so
+# that the default handler (trap_vector) is used.
+#ifndef __MACHINE_MODE
.align 2
.global stvec_handler
stvec_handler:
@@ -66,6 +70,7 @@ stvec_handler:
csrr t0, sepc
bne t0, t2, fail
j pass
+#endif
RVTEST_CODE_END