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| author | Neel <neelgala@gmail.com> | 2019-04-20 18:06:06 +0530 |
|---|---|---|
| committer | Neel <neelgala@gmail.com> | 2019-04-20 18:06:06 +0530 |
| commit | 266b2f950e43395e7e6ef5ec3a0d6494ce951edd (patch) | |
| tree | ff7ebeefa3cbf611de7e5e449d4844cb36302711 | |
| parent | d8177046a0809eb29241641c040eff81ead8a8de (diff) | |
| download | riscv-tests-266b2f950e43395e7e6ef5ec3a0d6494ce951edd.zip riscv-tests-266b2f950e43395e7e6ef5ec3a0d6494ce951edd.tar.gz riscv-tests-266b2f950e43395e7e6ef5ec3a0d6494ce951edd.tar.bz2 | |
fix for #159 #158
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 647430b..3e5e453 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -29,8 +29,9 @@ RVTEST_CODE_BEGIN la a2, 1f csrw tdata2, a2 - li a0, MCONTROL_M | MCONTROL_EXECUTE + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE csrw tdata1, a0 + andi a0, a0, 0x7ff # Skip if breakpoint type is unsupported. csrr a1, tdata1 andi a1, a1, 0x7ff @@ -47,8 +48,9 @@ RVTEST_CODE_BEGIN 2: # Set up breakpoint to trap on M-mode reads. li TESTNUM, 4 - li a0, MCONTROL_M | MCONTROL_LOAD + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD csrw tdata1, a0 + andi a0, a0, 0x7ff # Skip if breakpoint type is unsupported. csrr a1, tdata1 andi a1, a1, 0x7ff @@ -67,8 +69,9 @@ RVTEST_CODE_BEGIN 2: # Set up breakpoint to trap on M-mode stores. li TESTNUM, 6 - li a0, MCONTROL_M | MCONTROL_STORE + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_STORE csrw tdata1, a0 + andi a0, a0, 0x7ff # Skip if breakpoint type is unsupported. csrr a1, tdata1 andi a1, a1, 0x7ff @@ -94,7 +97,7 @@ RVTEST_CODE_BEGIN li a1, 2 bne a0, a1, pass - li a0, MCONTROL_M | MCONTROL_LOAD + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD csrw tdata1, a0 la a3, data2 csrw tdata2, a3 |