1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
|
#include <sys/time.h>
#include "devices.h"
#include "processor.h"
#define PLIC_MAX_CONTEXTS 15872
/*
* The PLIC consists of memory-mapped control registers, with a memory map
* as follows:
*
* base + 0x000000: Reserved (interrupt source 0 does not exist)
* base + 0x000004: Interrupt source 1 priority
* base + 0x000008: Interrupt source 2 priority
* ...
* base + 0x000FFC: Interrupt source 1023 priority
* base + 0x001000: Pending 0
* base + 0x001FFF: Pending
* base + 0x002000: Enable bits for sources 0-31 on context 0
* base + 0x002004: Enable bits for sources 32-63 on context 0
* ...
* base + 0x0020FC: Enable bits for sources 992-1023 on context 0
* base + 0x002080: Enable bits for sources 0-31 on context 1
* ...
* base + 0x002100: Enable bits for sources 0-31 on context 2
* ...
* base + 0x1F1F80: Enable bits for sources 992-1023 on context 15871
* base + 0x1F1F84: Reserved
* ... (higher context IDs would fit here, but wouldn't fit
* inside the per-context priority vector)
* base + 0x1FFFFC: Reserved
* base + 0x200000: Priority threshold for context 0
* base + 0x200004: Claim/complete for context 0
* base + 0x200008: Reserved
* ...
* base + 0x200FFC: Reserved
* base + 0x201000: Priority threshold for context 1
* base + 0x201004: Claim/complete for context 1
* ...
* base + 0xFFE000: Priority threshold for context 15871
* base + 0xFFE004: Claim/complete for context 15871
* base + 0xFFE008: Reserved
* ...
* base + 0xFFFFFC: Reserved
*/
/* Each interrupt source has a priority register associated with it. */
#define PRIORITY_BASE 0
#define PRIORITY_PER_ID 4
/*
* Each hart context has a vector of interupt enable bits associated with it.
* There's one bit for each interrupt source.
*/
#define ENABLE_BASE 0x2000
#define ENABLE_PER_HART 0x80
/*
* Each hart context has a set of control registers associated with it. Right
* now there's only two: a source priority threshold over which the hart will
* take an interrupt, and a register to claim interrupts.
*/
#define CONTEXT_BASE 0x200000
#define CONTEXT_PER_HART 0x1000
#define CONTEXT_THRESHOLD 0
#define CONTEXT_CLAIM 4
#define REG_SIZE 0x1000000
plic_t::plic_t(std::vector<processor_t*>& procs, bool smode, uint32_t ndev)
: procs(procs), contexts(procs.size() * (smode ? 2 : 1))
{
size_t contexts_per_hart = smode ? 2 : 1;
num_ids = ndev + 1;
num_ids_word = num_ids / 32;
if ((num_ids_word * 32) < num_ids)
num_ids_word++;
max_prio = (1UL << PLIC_PRIO_BITS) - 1;
memset(priority, 0, sizeof(priority));
memset(level, 0, sizeof(level));
for (size_t i = 0; i < contexts.size(); i++) {
plic_context_t* c = &contexts[i];
c->num = i;
c->proc = procs[i / contexts_per_hart];
if (smode) {
c->mmode = (i % contexts_per_hart == 0);
} else {
c->mmode = true;
}
memset(&c->enable, 0, sizeof(c->enable));
memset(&c->pending, 0, sizeof(c->pending));
memset(&c->pending_priority, 0, sizeof(c->pending_priority));
memset(&c->claimed, 0, sizeof(c->claimed));
}
}
uint32_t plic_t::context_best_pending(const plic_context_t *c)
{
uint8_t best_id_prio = 0;
uint32_t best_id = 0;
for (uint32_t i = 0; i < num_ids_word; i++) {
if (!c->pending[i]) {
continue;
}
for (uint32_t j = 0; j < 32; j++) {
uint32_t id = i * 32 + j;
if ((num_ids <= id) ||
!(c->pending[i] & (1 << j)) ||
(c->claimed[i] & (1 << j))) {
continue;
}
if (!best_id ||
(best_id_prio < c->pending_priority[id])) {
best_id = id;
best_id_prio = c->pending_priority[id];
}
}
}
return best_id;
}
void plic_t::context_update(const plic_context_t *c)
{
uint32_t best_id = context_best_pending(c);
reg_t mask = c->mmode ? MIP_MEIP : MIP_SEIP;
c->proc->state.mip->backdoor_write_with_mask(mask, best_id ? mask : 0);
}
uint32_t plic_t::context_claim(plic_context_t *c)
{
uint32_t best_id = context_best_pending(c);
uint32_t best_id_word = best_id / 32;
uint32_t best_id_mask = (1 << (best_id % 32));
if (best_id) {
c->claimed[best_id_word] |= best_id_mask;
}
context_update(c);
return best_id;
}
bool plic_t::priority_read(reg_t offset, uint32_t *val)
{
uint32_t id = (offset >> 2);
if (id > 0 && id < num_ids)
*val = priority[id];
else
*val = 0;
return true;
}
bool plic_t::priority_write(reg_t offset, uint32_t val)
{
uint32_t id = (offset >> 2);
if (id > 0 && id < num_ids) {
val &= ((1 << PLIC_PRIO_BITS) - 1);
priority[id] = val;
}
return true;
}
bool plic_t::context_enable_read(const plic_context_t *c,
reg_t offset, uint32_t *val)
{
uint32_t id_word = offset >> 2;
if (id_word < num_ids_word)
*val = c->enable[id_word];
else
*val = 0;
return true;
}
bool plic_t::context_enable_write(plic_context_t *c,
reg_t offset, uint32_t val)
{
uint32_t id_word = offset >> 2;
if (id_word >= num_ids_word)
return true;
uint32_t old_val = c->enable[id_word];
uint32_t new_val = id_word == 0 ? val & ~(uint32_t)1 : val;
uint32_t xor_val = old_val ^ new_val;
c->enable[id_word] = new_val;
for (uint32_t i = 0; i < 32; i++) {
uint32_t id = id_word * 32 + i;
uint32_t id_mask = 1 << i;
uint8_t id_prio = priority[id];
if (!(xor_val & id_mask)) {
continue;
}
if ((new_val & id_mask) &&
(level[id_word] & id_mask)) {
c->pending[id_word] |= id_mask;
c->pending_priority[id] = id_prio;
} else if (!(new_val & id_mask)) {
c->pending[id_word] &= ~id_mask;
c->pending_priority[id] = 0;
c->claimed[id_word] &= ~id_mask;
}
}
context_update(c);
return true;
}
bool plic_t::context_read(plic_context_t *c,
reg_t offset, uint32_t *val)
{
switch (offset) {
case CONTEXT_THRESHOLD:
*val = c->priority_threshold;
return true;
case CONTEXT_CLAIM:
*val = context_claim(c);
return true;
default:
return true;
};
}
bool plic_t::context_write(plic_context_t *c,
reg_t offset, uint32_t val)
{
bool ret = true, update = false;
switch (offset) {
case CONTEXT_THRESHOLD:
val &= ((1 << PLIC_PRIO_BITS) - 1);
if (val <= max_prio)
c->priority_threshold = val;
else
update = true;
break;
case CONTEXT_CLAIM: {
uint32_t id_word = val / 32;
uint32_t id_mask = 1 << (val % 32);
if ((val < num_ids) &&
(c->enable[id_word] & id_mask)) {
c->claimed[id_word] &= ~id_mask;
update = true;
}
break;
}
default:
ret = false;
update = true;
break;
};
if (update) {
context_update(c);
}
return ret;
}
void plic_t::set_interrupt_level(uint32_t id, int lvl)
{
if (id <= 0 || num_ids <= id) {
return;
}
uint8_t id_prio = priority[id];
uint32_t id_word = id / 32;
uint32_t id_mask = 1 << (id % 32);
if (lvl) {
level[id_word] |= id_mask;
} else {
level[id_word] &= ~id_mask;
}
/*
* Note: PLIC interrupts are level-triggered. As of now,
* there is no notion of edge-triggered interrupts. To
* handle this we auto-clear edge-triggered interrupts
* when PLIC context CLAIM register is read.
*/
for (size_t i = 0; i < contexts.size(); i++) {
plic_context_t* c = &contexts[i];
if (c->enable[id_word] & id_mask) {
if (lvl) {
c->pending[id_word] |= id_mask;
c->pending_priority[id] = id_prio;
} else {
c->pending[id_word] &= ~id_mask;
c->pending_priority[id] = 0;
c->claimed[id_word] &= ~id_mask;
}
context_update(c);
break;
}
}
}
bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
bool ret = false;
uint32_t val = 0;
switch (len) {
case 4:
break;
case 8:
// Implement double-word loads as a pair of word loads
return load(addr, 4, bytes) && load(addr + 4, 4, bytes + 4);
default:
// Subword loads are not supported
return false;
}
if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) {
ret = priority_read(addr, &val);
} else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) {
uint32_t cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART;
addr -= cntx * ENABLE_PER_HART + ENABLE_BASE;
if (cntx < contexts.size()) {
ret = context_enable_read(&contexts[cntx], addr, &val);
}
} else if (CONTEXT_BASE <= addr && addr < REG_SIZE) {
uint32_t cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART;
addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE;
if (cntx < contexts.size()) {
ret = context_read(&contexts[cntx], addr, &val);
}
}
if (ret) {
memcpy(bytes, (uint8_t *)&val, len);
}
return ret;
}
bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes)
{
bool ret = false;
uint32_t val;
switch (len) {
case 4:
break;
case 8:
// Implement double-word stores as a pair of word stores
return store(addr, 4, bytes) && store(addr + 4, 4, bytes + 4);
default:
// Subword stores are not supported
return false;
}
memcpy((uint8_t *)&val, bytes, len);
if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) {
ret = priority_write(addr, val);
} else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) {
uint32_t cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART;
addr -= cntx * ENABLE_PER_HART + ENABLE_BASE;
if (cntx < contexts.size())
ret = context_enable_write(&contexts[cntx], addr, val);
} else if (CONTEXT_BASE <= addr && addr < REG_SIZE) {
uint32_t cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART;
addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE;
if (cntx < contexts.size())
ret = context_write(&contexts[cntx], addr, val);
}
return ret;
}
|