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riscv-isa-sim.git
confprec
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cycleh
debug_rom
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device_flags
dtm_reset_error
dts_parsing
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eos18-bringup
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plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speed2
speedup-hacks
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mulw.h
blob: 81285a22cf11c6fcab64c57d7632671aac516d29 (
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1
2
RD
=
sext32
(
RS1
*
RS2
);
