c_flwsp.h\insns\riscv - riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

index : riscv-isa-sim.git

Unnamed repository; edit this file 'description' to name the repository.

root

about summary refs log tree commit diff

path: root/riscv/insns/c_flwsp.h

blob: eea0ec53ca814e0af01a45f2db6adff64186eaf4 (plain)

if (xlen == 32) {
  require_extension(EXT_ZCF);
  require_fp;
  WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm())));
} else { // c.ldsp
  require_extension(EXT_ZCA);
  require(insn.rvc_rd() != 0);
  WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm()));
}