aboutsummaryrefslogtreecommitdiff
path: root/riscv
AgeCommit message (Expand)AuthorFilesLines
2022-07-17Fix the initial value and write mask for mstatusWeiwei Li1-2/+6
2022-07-17remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIANWeiwei Li2-6/+0
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li2-9/+12
2022-07-15Split up misaligned store into several stepsScott Johnson1-2/+5
2022-07-15Split up misaligned load into several stepsScott Johnson1-2/+5
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman4-0/+10
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
2022-07-14add support for m/henvcfgh csrsWeiwei Li1-3/+15
2022-07-13Properly log mstatush side effect updatesScott Johnson3-2/+6
2022-07-13Add assertion to ensure proper logging of mstatus changes on RV32Scott Johnson1-0/+4
2022-07-13Use rv32_low_csr_t for Smstateen CSRsScott Johnson1-2/+8
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson3-1/+37
2022-07-13Remove no-longer-needed mask from rv32_high_csr_tScott Johnson2-3/+2
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson3-9/+7
2022-07-13Remove mstatush mask as unnecessaryScott Johnson1-1/+1
2022-07-13add check for H extension requires S mode (#1042)liweiwei902-1/+4
2022-07-13Add verify_permissions() for mseccfg_csr_tYenHaoChen2-0/+7
2022-07-13add isa string parser for smepmpYenHaoChen2-0/+3
2022-07-11Merge pull request #1035 from plctlab/plct-smstateen-devAndrew Waterman12-3506/+3644
2022-07-11Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (#1039)YenHaoChen1-1/+1
2022-07-09add smstateen check for fcsr, senvcfg, henvcfgWeiwei Li2-0/+44
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li3-2/+24
2022-07-09add support for csrs of smstateen extensionsWeiwei Li4-0/+106
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li3-13/+23
2022-07-07add isa string parser for smstateenWeiwei Li2-0/+3
2022-07-07update encoding.hWeiwei Li1-3381/+3444
2022-07-07remove multi blank linesWeiwei Li8-110/+0
2022-06-06Don't mask instruction bitsAndrew Waterman2-2/+2
2022-06-06Zero-extend instructions when fetching them from memoryAndrew Waterman1-4/+4
2022-06-06insn_t: don't rely on sign-extension of internal encodingAndrew Waterman1-3/+3
2022-06-03Remove nonstandard length encoding (#1023)Andrew Waterman1-1/+0
2022-06-01Remove the now-unused PC_SERIALIZE_WFIKip Walker2-3/+0
2022-05-26Fix RV32 hgatp write mask computation (#1014)Andrew Waterman1-1/+1
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome5-10/+25
2022-05-16Include recently added headers in riscv/riscv.mk.inPirmin Vogel1-0/+3
2022-05-13Merge pull request #997 from riscv-software-src/simplify-decode_insnAndrew Waterman3-19/+18
2022-05-12Remove now-unnecessary null check from decode_insnAndrew Waterman1-2/+2
2022-05-12Assert that nullptrs can't make their way into the instructions listAndrew Waterman1-0/+2
2022-05-12Remove insn_func_t::supported fieldAndrew Waterman3-10/+5
2022-05-12Don't register instructions that aren't supportedAndrew Waterman1-8/+10
2022-05-11Merge pull request #992 from rbuchner-aril/rb-pbmteAndrew Waterman4-6/+37
2022-05-11Check for reserved PBMT values during tablewalks and fault if foundRyan Buchner1-0/+4
2022-05-11Switch from checking for SVPBMT extension to checking *ENVCFG values during t...Ryan Buchner1-2/+4
2022-05-11Add PBMTE bit to menvcfg and henvcfg mask valuesRyan Buchner1-4/+8
2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner3-1/+22
2022-05-11rvv: fix the checking eew and elen for index loadChih-Min Chao1-0/+1
2022-05-05Factor out P extension macros into their own headerfactor-out-macrosAndrew Waterman2-500/+507
2022-05-05Factor out V extension macros into their own headerAndrew Waterman2-2069/+2076
2022-05-05Merge pull request #983 from soberl/epmp_updates_2Scott Johnson5-13/+130
2022-05-04Update pmpaddr_csr_t::access_ok() for ePMP on matching regionssoberl@nvidia.com1-5/+31
generated by cgit v1.1 at 2024-08-07 12:13:39 +0000