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path: root/riscv/sim.h
AgeCommit message (Expand)AuthorFilesLines
2012-05-15fix htif interaction with interactive modeAndrew Waterman1-4/+1
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-5/+0
2012-03-24new supervisor modeAndrew Waterman1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+82
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-66/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-0/+1
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-4/+3
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-0/+3
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-1/+1
2011-04-16[sim] added "str" debug commandAndrew Waterman1-0/+1
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+2
2010-09-08[sim] add while to interactive_untilYunsup Lee1-12/+13
2010-09-06[sim] fixed bug in msub.d; added ability to print FPRs in debug modeAndrew Waterman1-0/+3
2010-08-09[sim] removed unused elf loaderAndrew Waterman1-1/+0
2010-07-21[pk,sim] first cut of appserver communication linkAndrew Waterman1-5/+16
2010-07-18Reorganized directory structureAndrew Waterman1-0/+46
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