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2024-06-11Separate RV32 and RV64 C instructions into separate filesAndrew Waterman1-0/+4
2024-06-11Compensate for perf loss of not mutating insn list by presorting itAndrew Waterman1-7/+7
2024-06-11Add missing instructions to MakefileAndrew Waterman1-0/+4
2024-05-06Add Zawrs extensionVed Shanbhogue1-0/+5
2024-05-01Remove Zbpbo, Zpn, and Zpsfoperand implementationAndrew Waterman1-336/+0
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-0/+12
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page.
2024-03-06Zicfilp: Implement lpad insn behaviorMing-Yi Lai1-0/+4
2024-03-03Don't include subproject headers with -IAndrew Waterman1-1/+1
Use -iquote instead. This prevents our include paths from messing up the system headers depended upon by libstdc++. (The specific problem was syscall.h in fesvr/, which was interfering with libstdc++'s dependence on the system's syscall.h for SYS_futex.) Subproject headers can now be included in the following ways: #include "foo.h" // for a header local to this subproject #include <bar/baz.h>" // for a header in another subproject But no longer: #include <baz.h> // for a header in any subproject As a special case, libfdt needs itself to be added to the -I path, because their coding style is to use angle brackets for local headers.
2023-12-08Add Zimop extensionAndrew Waterman1-0/+5
2023-11-02Add Zabha instructions to makeVed Shanbhogue1-0/+23
2023-10-18Spike support for the Zalasr extensionbrs1-0/+11
2023-10-16vamo: remove from building listChih-Min Chao1-39/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2023-07-11Move isa_parser_t to libdisasm out of libriscvJerry Zhao1-1/+0
2023-06-20devices: Switch plugin device interface to use device_factory_tJerry Zhao1-1/+0
Plugins should now implement and register a device_factory_t to configure how that device should be parsed from a FDT, and an optional default DTS string. This drops support for command-line flag-based device configuration
2023-06-20dts_t: Add dts.h to list of installed headersJerry Zhao1-0/+1
2023-06-19Zvk: Implement Zvksh, vector SM3 Hash FunctionEric Gouriou1-0/+5
Implement the Zvksh sub-extension, "ShangMi Suite: SM3 Hash Function Instructions": - vsm3me.vv, message expansion, - vsm3c.vi, compression rounds. This also introduces a SM3 specific header for common logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Co-authored-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvksed, vector SM4 Block CipherEric Gouriou1-0/+6
Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher": - vsm4k.vi, vector SM4 key expansion, - vsm4r.{vs,vv}, vector SM4 rounds. This also introduces a header for common vector SM4 logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkned, vector AES single roundEric Gouriou1-0/+14
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption & Decryption (Single Round)". - vaeskf1.vi: AES forward key scheduling, AES-128. - vaeskf2.vi: AES forward key scheduling, AES-256. - vaesz.vs: AES encryption/decryption, 0-th round. - vaesdm.{vs,vv}: AES decryption, middle rounds. - vaesdf.{vs,vv}: AES decryption, final round. - vaesem.{vs,vv}: AES encryption, middle rounds. - vaesef.{vs,vv}: AES encryption, final round. An extension specific header containing common logic is added. Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvknh[ab], NIST Suite: Vector SHA-2Eric Gouriou1-0/+7
Implement the instructions part of the Zvknha and Zvknhb sub-extensions: - vsha2ms.vv, message schedule - vsha2ch.vv / vsha2cl.vv, compression rounds A header files for common macros is added. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkg, Vector GCM/GMAC instructionEric Gouriou1-0/+5
Implement the proposed instruction in Zvkg, vghmac.vv, Vector Carryless Multiply Accumulate over GHASH Galois-Field. The instruction performs one step of GHASH routine as described in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification. The logic was written to closely track the pseudo-code in the Zvk specification. Signed-off-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbc extension, vectory carryless multiplactionEric Gouriou1-0/+7
Implement the Zvbc instructions - vclmul.{vv,vx}, vector carryless multiply low - vclmulh.{vv,vx}, vector carryless multiply high Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbb, Vector Bit-manipulation for CryptographyEric Gouriou1-0/+22
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19List extensions alphabetically in riscv_insn_listEric Gouriou1-16/+16
The previous order lacks any obvious logic. Alphabetical order, while making it difficult to create interesting groupings, makes it easy to find which extensions are compiled in. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Implement Zacas extension.Gianluca Guida1-0/+6
2023-06-18Remove instructions that belong only to XbitmanipAndrew Waterman1-42/+0
2023-06-17Add test that ensures opcodes don't overlap unless explicitly specifiedAndrew Waterman1-1/+2
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li1-0/+5
2023-05-29Add support for new instructions of Zvfbfmin extensionWeiwei Li1-0/+5
2023-05-29Add support for new instructions of Zfbfmin extensionWeiwei Li1-2/+10
2023-05-19Add Spike's meta files for pkg-configWojciech Bartczak1-0/+2
This commit adds the *.pc files for Spike's simulation library, enabling dynamic and static linking without the need to directly reference Spike sources. Using Spike as a stand-alone library provides an interesting option for developing tools and applications based on Spike.
2023-04-12Add debug_defines.h to list of installed headersJerry Zhao1-0/+1
2023-04-03Implement Zfa.Philipp Tomsich1-0/+45
This passes our developer test suite, when comparing output (signature) against the SAIL implementation. If any corner-cases require additional changes after ACT goes upstream, we can apply an add-on patch.
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+4
We don't model any sources of RNMI, so this is mostly vestigial.
2023-02-04Add disasm/extension/rocc.h to installed headersJerry Zhao1-0/+3
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich1-0/+5
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
2022-12-22Remove non-installed header lists from Makefile fragmentsAndrew Waterman1-34/+0
It's just dead code. (Dependences on headers are auto-generated as `.d` files.)
2022-12-20Reduce compile time increase introduced by #1189Andrew Waterman1-13/+4
Generate one object file per instruction rather than two, which reduces the overhead of invoking the compiler so many times. This also reduces the size of the (unstripped) binary substantially.
2022-12-20Add logged variants of insn templatesJerry Zhao1-5/+13
2022-12-16Add missing vector_unit.h to install headers listJerry Zhao1-1/+2
2022-12-16Add missing abstract_interrupt_controller.h to header listsJerry Zhao1-0/+2
2022-12-15Don't install instruction decode macrosJerry Zhao1-3/+1
2022-12-15Merge pull request #1180 from ucb-bar/cleancfgAndrew Waterman1-0/+1
Pull mmu.h out of cfg.h
2022-12-15Add cfg.cc to hold internal implementation of mem_cfg_tJerry Zhao1-0/+1
2022-12-15Split decode.h into public decode.h and private decode_macros.hJerry Zhao1-0/+1
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h
2022-12-13Move boost asio socket interface to socketif_tJerry Zhao1-1/+3
This reduces dependencies on config.h in sim.h
2022-12-12Pull vector unit into separate source/headerJerry Zhao1-0/+2
2022-11-17add support for zcmtWeiwei Li1-0/+4
add suport for jvt: Table entries follow the current data endianness
2022-11-17add support for zcmpWeiwei Li1-0/+9
2022-11-17add support for zcbWeiwei Li1-1/+19
2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman1-1/+34
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