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2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0
Resolves #308
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+1
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-06-18rvv: add floating-point instructionsChih-Min Chao1-0/+96
based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add load/store instructionsChih-Min Chao1-0/+47
based on v-spec 0.7.1, support section: 7 element size: 8/16/32/64 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+206
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+8
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-09rvv: re-arrange instruction list by different extensionChih-Min Chao1-129/+155
It is preparatory commit for vector extension. v-ext has hundresds of new instructions and mixing them with scalar instructions messes up code. Separate each extension into different list to make thing clean Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-0/+1
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-0/+2
2017-09-28Implement Q extensionAndrew Waterman1-0/+32
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-2/+4
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-2/+2
2017-04-17debug: Compiles again with new debug_defines.h file, but not tested.Megan Wachs1-2/+0
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-1/+3
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-1/+1
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-1/+1
2017-02-06Refactor remote bitbang code.Tim Newsome1-0/+2
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-2/+2
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-2/+0
2016-05-23Add dret.Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-0/+2
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+2
So far it just listens, and gdb times out because it's not getting any messages back. Receive packets and verify their checksum.
2016-05-19Removed devicetree.h from riscv.mk.in since it no longer existsacw12511-1/+0
2016-05-18Added missing header files to riscv.mk.inacw12511-0/+3
Merges #40
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-0/+2
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman1-2/+3
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+0
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+1
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman1-2/+0
2015-10-05more work towards RVC 1.8Andrew Waterman1-2/+0
2015-10-02work towards rvc 1.8Andrew Waterman1-1/+11
2015-09-10Fix non-portable sed commands generating insn_list.hAlbert Ou1-1/+3
2015-09-08Improve instruction fetchAndrew Waterman1-1/+200
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
2015-05-13Install "disasm.h"Palmer Dabbelt1-0/+1
Something includes this somewhere, so I see no reason not to just install it.
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-1/+2
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-2/+4
In particular, precompiled headers ideally won't depend on any.
2014-11-25Factor out the dummy RoCC acceleratorAndrew Waterman1-1/+0
2014-11-19Add missing makefile dependenceAndrew Waterman1-1/+2
This manifested as a spurious compile warning when using make -j.
2014-09-27Avoid some unused variable warningsAndrew Waterman1-2/+3
...and also save some space by not defining the register names in a header.
2014-09-27Avoid use of __int128_tAndrew Waterman1-0/+1
It is nonstandard, and GCC doesn't support it on 32-bit platforms. The resulting code for MULH[[S]U] is crappier, but that doesn't really matter, as these instructions are dynamically infrequent.
2014-07-07Use precompiled headers to speed up compilationAndrew Waterman1-0/+4
2014-01-26Eliminate hwacha <-> riscv circular dependenceAndrew Waterman1-5/+0
We now split out the spike executable into another subproject, which depends on both rocket and hwacha
2014-01-25Merge softfloat_riscv into softfloatAndrew Waterman1-1/+0
They really aren't independent libraries.
2014-01-13Improve performance for branchy codeAndrew Waterman1-0/+4
We now use a heavily unrolled loop as the software I$, which allows the host machine's branch target prediction to associate target PCs with unique-ish host PCs.
2013-11-25Update to new privileged ISAAndrew Waterman1-5/+5
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee1-0/+1
2013-09-15Add helper disassembly programAndrew Waterman1-0/+1
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