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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 13:57:56 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-22 14:21:54 -0700 |
| commit | 46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb (patch) | |
| tree | 1ff563929c13be279340ad439af8692d3c9913aa /riscv/riscv.mk.in | |
| parent | 693fc45eb8ccc3c9f84b898de3119a172e0776f5 (diff) | |
| download | riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.zip riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.gz riscv-isa-sim-46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb.tar.bz2 | |
riscv: replace rtc device with a real clint implementation
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 17479dc..e954416 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -44,7 +44,7 @@ riscv_srcs = \ regnames.cc \ devices.cc \ rom.cc \ - rtc.cc \ + clint.cc \ gdbserver.cc \ debug_module.cc \ $(riscv_gen_srcs) \ |