Age | Commit message (Expand) | Author | Files | Lines |
2019-07-16 | Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311) | Tim Newsome | 1 | -1/+1 |
2019-07-12 | Add debug_mode state bit, rather than overloading dcsr.cause | Andrew Waterman | 1 | -2/+4 |
2019-06-14 | rvv: add varch option parser and initialize vector unit | Chih-Min Chao | 1 | -1/+3 |
2019-06-14 | rvv: add vector unit structure | Chih-Min Chao | 1 | -0/+118 |
2018-09-25 | Add PMP support | Andrew Waterman | 1 | -0/+4 |
2018-07-10 | Refactor and fix LR/SC implementation (#217) | Andrew Waterman | 1 | -3/+0 |
2018-03-21 | Implement Hauser misa.C misalignment proposal (#187) | Andrew Waterman | 1 | -1/+4 |
2018-03-14 | Fix a bug caused by moving misa into state_t. (#180) | Prashanth Mundkur | 1 | -1/+1 |
2018-03-13 | Move processor.isa to state.misa, since it really belongs there. | Prashanth Mundkur | 1 | -2/+2 |
2018-03-06 | Narrow the interface used by the processors and memory to the top-level simul... | Prashanth Mundkur | 1 | -4/+5 |
2018-03-06 | Fix install of a missed header from debug_rom. | Prashanth Mundkur | 1 | -1/+1 |
2018-03-03 | Implement clearing-misa.C-while-PC-is-misaligned proposal | Andrew Waterman | 1 | -0/+5 |
2017-11-27 | Rename badaddr to tval | Andrew Waterman | 1 | -2/+2 |
2017-11-27 | Rename sptbr to satp | Andrew Waterman | 1 | -1/+1 |
2017-11-09 | H-mode no longer exists | Andrew Waterman | 1 | -1/+0 |
2017-11-09 | MPP is now WARL | Andrew Waterman | 1 | -0/+1 |
2017-10-20 | Fix commit-log for Q extension, and for RV32 (#143) | Andrew Waterman | 1 | -1/+9 |
2017-09-21 | Fix corner case in repeated execution (#127) | Tim Newsome | 1 | -0/+3 |
2017-08-07 | Fix multicore debug. | Tim Newsome | 1 | -6/+0 |
2017-04-18 | debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b... | Megan Wachs | 1 | -0/+1 |
2017-04-17 | debug: Move things around, but addresses now conflict with ROM. | Megan Wachs | 1 | -0/+1 |
2017-04-17 | Merge remote-tracking branch 'origin/priv-1.10' into HEAD | Megan Wachs | 1 | -6/+5 |
2017-03-22 | riscv: replace rtc device with a real clint implementation | Wesley W. Terpstra | 1 | -1/+1 |
2017-02-25 | New counter enable scheme | Andrew Waterman | 1 | -2/+2 |
2017-02-10 | Entering debug mode now jumps to "dynamic rom" | Tim Newsome | 1 | -0/+6 |
2017-02-10 | Implement hartstatus field. | Tim Newsome | 1 | -0/+1 |
2017-02-02 | Fix interrupt delegation for coprocessors | Andrew Waterman | 1 | -3/+2 |
2016-09-09 | allow MAFDC bits in MISA to be modified | Andrew Waterman | 1 | -0/+1 |
2016-09-02 | Merge branch 'master' into trigger | Tim Newsome | 1 | -2/+2 |
2016-08-31 | Rename tdata[0-2] to tdata[1-3]. | Tim Newsome | 1 | -12/+14 |
2016-08-29 | Rename tdata0--tdata2 to tdata1--tdata3. | Tim Newsome | 1 | -0/+1 |
2016-08-26 | Add (degenerate) performance counter facility | Andrew Waterman | 1 | -2/+2 |
2016-08-25 | partially update spike to newer debug spec | Andrew Waterman | 1 | -25/+16 |
2016-08-25 | Fix spike interactive (-d) mode | Andrew Waterman | 1 | -3/+2 |
2016-08-22 | Implement address and data triggers. | Tim Newsome | 1 | -1/+151 |
2016-08-17 | Allow mstatus.MPP to store bad values; instead, validate on MRET | Andrew Waterman | 1 | -1/+0 |
2016-07-28 | Add support for virtual priv register. (#59) | Tim Newsome | 1 | -0/+1 |
2016-06-29 | Disassemble RVC instructions based on XLEN | Andrew Waterman | 1 | -0/+1 |
2016-06-22 | Remove legacy HTIF; implement HTIF directly | Andrew Waterman | 1 | -3/+1 |
2016-06-22 | Fix paddr_bits computation prior to VM setup | Andrew Waterman | 1 | -0/+1 |
2016-05-23 | Make -H halt the core right out of reset. | Tim Newsome | 1 | -1/+2 |
2016-05-23 | Single step appears to work. | Tim Newsome | 1 | -0/+8 |
2016-05-23 | processor_t unfriends gdbserver_t. | Tim Newsome | 1 | -3/+3 |
2016-05-23 | Add debug_module bus device. | Tim Newsome | 1 | -2/+0 |
2016-05-23 | When gdb connects, jump to Debug ROM and segfault. | Tim Newsome | 1 | -9/+1 |
2016-05-23 | Gutting direct-access gdb. | Tim Newsome | 1 | -8/+2 |
2016-05-23 | Add writing to DCSR, DPC, DSCRATCH. | Tim Newsome | 1 | -0/+17 |
2016-05-23 | Flush icache when using swbps and report to gdb. | Tim Newsome | 1 | -1/+11 |
2016-05-23 | Looks like single step works. | Tim Newsome | 1 | -0/+4 |
2016-05-23 | Now you can halt/continue from gdb. | Tim Newsome | 1 | -0/+4 |