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2024-04-29add hlvx pmp protect to fix issue 1557xinyuwang-sifive1-3/+3
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-1/+31
2024-01-24Use designated initiallizers to construct xlate_flags_t objectsrbuchner1-27/+15
2023-08-27report right pseudo-inst for guest PF caused for VS-stage addr transVed Shanbhogue1-1/+1
2023-07-19Merge pull request #1413 from YenHaoChen/pr-mcontrol-cbo-zero-tvalAndrew Waterman1-2/+10
2023-07-19mcontrol/mcontrol6 triggers on cbo.flush/cleanYenHaoChen1-0/+3
2023-07-18mmu: fetch instruction bytes in ascending orderYinan Xu1-3/+3
2023-07-13fix mcontrol's tval on cbo_zeroYenHaoChen1-1/+3
2023-07-13refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameterYenHaoChen1-1/+4
2023-06-19Implement Zacas extension.Gianluca Guida1-0/+11
2023-06-12Fix PMP checking region of cache-block management instructionsYenHaoChen1-1/+1
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-1/+1
2023-05-11Add split_misaligned_access() to mem_access_info_trbuchner1-0/+4
2023-05-11Pass mem_access_info_t into walk()rbuchner1-1/+1
2023-05-11Adjust store_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-1/+1
2023-05-11Adjust load_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-1/+1
2023-05-11Add structure (mem_access_info_t) for holding memory access informationRyan Buchner1-3/+31
2023-05-11Add is_special_access() to xlate_flags_trbuchner1-2/+6
2023-05-11Add xlate_flags_t structrbuchner1-21/+35
2023-05-11Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRTRyan Buchner1-4/+4
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+1
2023-03-16Make MPRV logic consistent; factor it outAndrew Waterman1-0/+7
2023-03-04Don't issue misaligned or non-power-of-2 MMIO accessesScott Johnson1-0/+1
2023-02-20Rename host_pte_paddr to host_pte_addrScott Johnson1-6/+6
2023-02-04Use relative path for fesvr/byteorder.h in mmu.hJerry Zhao1-1/+1
2023-01-27Remove dirty_enabled from cfg_tAaron Durbin1-2/+0
2023-01-04Respect --mmu-dirty flag instead of --enable-dirtyJerry Zhao1-8/+1
2023-01-03Respect --[no-]misaligned command-line flagAndrew Waterman1-11/+7
2023-01-03Merge pull request #1200 from riscv-software-src/mmio_pteAndrew Waterman1-0/+49
2023-01-03Support pte load/store from mmio regionsJerry Zhao1-2/+2
2023-01-03Pull pte load/store into methods of mmu_tJerry Zhao1-0/+49
2023-01-03Add method to probe which memory regions are reservableJerry Zhao1-3/+3
2023-01-03Specify addresses are physical for simif_t member functionsJerry Zhao1-4/+4
2022-12-23Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accessesJerry Zhao1-0/+1
2022-12-20Replace compile-time conditional with run-time conditional for load/store log...Jerry Zhao1-19/+4
2022-12-15Rename memif_endianness_t to endianness_tJerry Zhao1-1/+1
2022-12-15Pull memif_endianness_t into cfg.hJerry Zhao1-0/+1
2022-11-28Restore fetch_jump_table to instruction fetchWeiwei Li1-3/+2
2022-11-17add support for zcmtWeiwei Li1-0/+7
2022-10-25Remove set_target_endianness | add --big-endian flagJerry Zhao1-10/+1
2022-10-20Merge pull request #1122 from riscv-software-src/more-mmu-simplificationAndrew Waterman1-101/+82
2022-10-20Use reg_t, not uint64_t, for address-like quantitiesAndrew Waterman1-2/+2
2022-10-20Fix tval reporting for CBOsAndrew Waterman1-2/+1
2022-10-19Template-ize storesAndrew Waterman1-13/+3
2022-10-19Template-ize loadsAndrew Waterman1-17/+1
2022-10-19Template-ize AMOsAndrew Waterman1-14/+9
2022-10-19DRY in store-conditional instructionsAndrew Waterman1-0/+13
2022-10-19Simplify check_load_reservationAndrew Waterman1-2/+2
2022-10-19Template-ize hypervisor loads and storesAndrew Waterman1-20/+15
2022-10-19Remove require_alignment flag from loadsAndrew Waterman1-5/+5
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