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AgeCommit message (Expand)AuthorFilesLines
2019-12-20rvv: make vlx/vsx match 0.8 specChih-Min Chao11-30/+17
2019-12-20rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao2-2/+2
2019-12-20rvv: fix vmadc/vmsbcChih-Min Chao5-5/+5
2019-12-20rvv: fix vadc/vsbcChih-Min Chao5-15/+10
2019-12-20rvv: add unsigned averageChih-Min Chao4-0/+8
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao12-0/+0
2019-12-20rvv: fix floating sign inject operand orderChih-Min Chao6-6/+6
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao2-0/+20
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao6-3/+10
2019-12-20rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao14-14/+35
2019-12-16Simplify vleff.v implementation in the same way as vle.vAndrew Waterman1-53/+11
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna1-0/+1
2019-11-12SRET requires S-modeAndrew Waterman1-0/+1
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao13-74/+51
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao16-5/+20
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao17-4/+17
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao10-10/+10
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao18-18/+18
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao15-86/+34
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao2-23/+20
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao1-22/+25
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao5-5/+5
2019-10-29rvv: remove vmfordChih-Min Chao2-10/+0
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman23-13/+23
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman2-0/+2
2019-07-19Avoid relying on sizeof longAndrew Waterman3-5/+5
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman2-30/+25
2019-07-12DRET should not be legal in M-modeAndrew Waterman1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-1/+1
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman2-0/+0
2019-06-18rvv: add floating-point instructionsChih-Min Chao81-0/+509
2019-06-18rvv: add load/store instructionsChih-Min Chao44-0/+371
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao215-0/+2226
2019-06-18rvv: add control instructions and system register accessChih-Min Chao2-0/+2
2018-11-06Report misaligned-address exception on failed store-conditionalsAndrew Waterman2-14/+8
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman4-4/+8
2018-05-04Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"Andrew Waterman2-0/+2
2018-05-03C.LWSP and C.LDSP with rd=0 are legal instructionsAndrew Waterman2-2/+0
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman1-1/+1
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instr...Andrew Waterman3-3/+3
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ...Shubhodeep Roy Choudhury3-3/+3
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman6-0/+6
2017-10-19Fix implementation of FMIN/FMAX NaN caseAndrew Waterman6-6/+12
2017-09-28Implement Q extensionAndrew Waterman40-8/+163
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