| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-11-11 | rvv: fix vsmul sign and variable type | Chih-Min Chao | 1 | -12/+11 | |
| Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2019-07-19 | Avoid relying on sizeof long | Andrew Waterman | 1 | -2/+2 | |
| 2019-06-18 | rvv: add integer/fixed-point/mask/reduction/permutation instructions | Chih-Min Chao | 1 | -0/+33 | |
| based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> | |||||
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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