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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-08 01:25:18 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:34 -0800 |
commit | 8f555c55a7643dcf06e91622c26fdbfbcc91433c (patch) | |
tree | 2912f94bfdb089d56d0c8d12c16f126af79200ed /riscv/insns/vsmul_vv.h | |
parent | 3ccf946e6d814203733a7804b9f9b7b99e38255f (diff) | |
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rvv: fix vsmul sign and variable type
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsmul_vv.h')
-rw-r--r-- | riscv/insns/vsmul_vv.h | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index a0c7f99..0807899 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -1,33 +1,32 @@ // vsmul: Signed saturating and rounding fractional multiply VRM xrm = P.VU.get_vround_mode(); -uint64_t int_max = (uint64_t(1) << (P.VU.vsew - 1)) - 1; -uint64_t int_min = - (1 << (P.VU.vsew - 1)); -uint64_t sign_mask = uint64_t(1) << (P.VU.vsew - 1); +int64_t int_max = (uint64_t(1) << (P.VU.vsew - 1)) - 1; +int64_t int_min = - (1 << (P.VU.vsew - 1)); +int64_t sign_mask = uint64_t(1) << (P.VU.vsew - 1); -VI_VV_ULOOP +VI_VV_LOOP ({ - uint64_t vs1_sign; - uint64_t vs2_sign; - uint64_t result_sign; + int64_t vs1_sign; + int64_t vs2_sign; + int64_t result_sign; vs1_sign = vs1 & sign_mask; vs2_sign = vs2 & sign_mask; bool overflow = vs1 == vs2 && vs1 == int_min; - uint128_t result = (uint128_t)vs1 * (uint128_t)vs2; - result &= ((uint128_t)1llu << ((sew * 2) - 2)) - 1; + int128_t result = (int128_t)vs1 * (int128_t)vs2; result_sign = (vs1_sign ^ vs2_sign) & sign_mask; + // rounding INT_ROUNDING(result, xrm, sew - 1); - // unsigned shifting + // remove guard bits result = result >> (sew - 1); // saturation if (overflow) { result = int_max; P.VU.vxsat = 1; - } else { - result |= result_sign; } + vd = result; }) |