| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-01-22 | commitlog: rvv: add commitlog support to misc instrutions | Chih-Min Chao | 1 | -4/+4 |
| 2019-11-11 | rvv: add reg checking for specifial instructions | Chih-Min Chao | 1 | -15/+8 |
| 2019-11-11 | rvv: remove configuable tail-zero | Chih-Min Chao | 1 | -1/+1 |
| 2019-07-19 | Check vtype.vill for all vector instructions except vsetvl[i] | Andrew Waterman | 1 | -1/+1 |
| 2019-06-18 | rvv: add integer/fixed-point/mask/reduction/permutation instructions | Chih-Min Chao | 1 | -0/+41 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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