| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-11-12 | SRET requires S-mode | Andrew Waterman | 1 | -0/+1 |
| 2017-03-16 | Simplify interrupt-stack discipline | Andrew Waterman | 1 | -1/+1 |
| 2017-03-13 | Implement mstatus.TW, mstatus.TVM, and mstatus.TSR | Andrew Waterman | 1 | -1/+1 |
| 2017-02-01 | Set xPIE=1 on xRET | Andrew Waterman | 1 | -1/+1 |
| 2016-05-23 | Add dret. | Tim Newsome | 1 | -3/+0 |
| 2016-05-23 | Properly save/restore dpc, mcause, mbadaddr. | Tim Newsome | 1 | -0/+3 |
| 2016-04-19 | Split ERET into URET, SRET, HRET, MRET | Andrew Waterman | 1 | -13/+6 |
| 2016-03-02 | Fix ERET bug | Andrew Waterman | 1 | -1/+1 |
| 2016-03-02 | Serialize simulator on ERET | Andrew Waterman | 1 | -2/+2 |
| 2016-03-02 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -2/+10 |
| 2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 1 | -1/+6 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -5/+3 |
| 2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -0/+5 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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