riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-10-14	Split 'P' to EXT_ZPN and friends (#830)	marcfedorow	1	-1/+1
2015-04-03	Support setting ISA/subsets with --isa flag	Andrew Waterman	1	-0/+1
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-1/+1
2014-09-27	Avoid use of __int128_t	Andrew Waterman	1	-6/+2
2013-09-27	Use WRITE_RD/WRITE_FRD macros to write registers	Andrew Waterman	1	-2/+2
2011-06-19	temporary undoing of renaming	Andrew Waterman	1	-0/+8
2011-06-12	[sim] renamed to riscv-isa-run	Andrew Waterman	1	-8/+0
2011-04-16	[sim] removed undefined behavior for non-canonical inputs	Andrew Waterman	1	-1/+1
2011-01-18	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	1	-4/+8
2010-11-21	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	1	-1/+1
2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-3/+3
2010-08-03	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	1	-2/+4
2010-07-28	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	1	-0/+2