riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2015-04-03	Support setting ISA/subsets with --isa flag	Andrew Waterman	1	-0/+1
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-1/+1
2013-09-27	Use WRITE_RD/WRITE_FRD macros to write registers	Andrew Waterman	1	-2/+2
2012-02-15	reimplement div[u][w]/rem[u][w]	Andrew Waterman	1	-4/+4
2012-01-30	fix divide by zero bugs	Yunsup Lee	1	-1/+1
2011-06-19	temporary undoing of renaming	Andrew Waterman	1	-0/+7
2011-06-12	[sim] renamed to riscv-isa-run	Andrew Waterman	1	-7/+0
2011-04-23	[sim] fixed divw/remw crashing simulator	Andrew Waterman	1	-3/+1
2011-04-16	[sim] removed undefined behavior for non-canonical inputs	Andrew Waterman	1	-1/+1
2011-01-26	[sim] changed divide-by-0 semantics	Andrew Waterman	1	-2/+4
2011-01-18	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	1	-3/+6
2010-12-27	[sim] fixed some compiler warnings	Andrew Waterman	1	-1/+1
2010-11-21	[sim] handle integer division overflow	Andrew Waterman	1	-2/+4
2010-11-21	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	1	-1/+1
2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-1/+1
2010-08-03	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	1	-0/+2