riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-05-23	gdb can attach and read the PC:	Tim Newsome	1	-1/+1
2016-05-23	processor_t unfriends gdbserver_t.	Tim Newsome	1	-2/+2
2016-05-23	Add debug_module bus device.	Tim Newsome	1	-1/+10
2016-05-23	When gdb connects, jump to Debug ROM and segfault.	Tim Newsome	1	-0/+4
2016-05-23	Gutting direct-access gdb.	Tim Newsome	1	-13/+1
2016-05-23	Flush icache when using swbps and report to gdb.	Tim Newsome	1	-2/+2
2016-05-23	Software breakpoints seem to work.	Tim Newsome	1	-4/+1
2016-05-23	Looks like single step works.	Tim Newsome	1	-1/+14
2016-05-23	Now you can halt/continue from gdb.	Tim Newsome	1	-1/+3
2016-03-02	Return to interactive mode after a trap	Andrew Waterman	1	-0/+1
2016-03-02	Fix ERET serialization strategy	Andrew Waterman	1	-4/+7
2016-03-02	WIP on priv spec v1.9	Andrew Waterman	1	-1/+1
2015-10-26	Fix histogram for RVC	Andrew Waterman	1	-3/+2
2015-09-15	commit log now correctly prints privilege	Scott Beamer	1	-3/+12
2015-09-11	print out current privilege level (if commit log enabled)	Scott Beamer	1	-2/+4
2015-09-11	print out commit log (if enabled) for all privilege levels	Scott Beamer	1	-12/+10
2015-09-08	Improve instruction fetch	Andrew Waterman	1	-0/+117