| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-10-07 | Speed up compilation of disasm.cc, especially in clang | Andrew Waterman | 1 | -2/+2 |
| 2019-06-18 | rvv: add simple instruction parsing tool | Chih-Min Chao | 1 | -1/+9 |
| 2019-06-14 | rvv: disasm: add v-spec 0.7.1 support | Chih-Min Chao | 1 | -3/+22 |
| 2019-06-14 | disams: make instruction name dynamic | Chih-Min Chao | 1 | -1/+2 |
| 2018-03-26 | Add an api to get the name for a CSR. | Prashanth Mundkur | 1 | -0/+1 |
| 2016-06-29 | Disassemble RVC instructions based on XLEN | Andrew Waterman | 1 | -3/+3 |
| 2014-09-27 | Avoid some unused variable warnings | Andrew Waterman | 1 | -13/+2 |
| 2014-07-24 | added support for register convention names in debug mode | Scott Beamer | 1 | -0/+14 |
| 2013-10-18 | refactor disassembler, and add hwacha disassembler | Yunsup Lee | 1 | -5/+50 |
| 2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 |
| 2011-11-11 | Remove dependence on binutils | Your Name | 1 | -0/+23 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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