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2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman1-0/+3
2022-10-16Add interactive mode commands to read clint mtime/mtimecmpJerry Zhao1-0/+2
2022-10-14Add dump memory command to interactive modeJerry Zhao1-0/+1
2022-04-20Add ns16550 serial device emulationAnup Patel1-0/+31
The ns16550 is a widely use serial device so we add a simplified ns16550 device emulation which is good enough for Linux, OpenSBI, and hypervisors to use as console. Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-20Add PLIC emulationAnup Patel1-0/+45
We need an interrupt controller in Spike which will allow us to emulate more real-world devices such as UART, VirtIO net, VirtIO block, etc. The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt controller in existing RISC-V platforms so this patch adds PLIC emulation for Spike. Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-20Add an abstract interrupt controller interfaceAnup Patel1-0/+1
We add an abstract interrupt controller interface which can be used by devices to trigger wired interrupts. Signed-off-by: Anup Patel <anup@brainfault.org>
2021-06-04encoding: udpate and move platform-related define outChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-04Refactor headersAndrew Waterman1-9/+1
2021-02-04Fix --kernel and --initrd options w.r.t. sparse mem_t implementationAndrew Waterman1-16/+9
For some reason, the old accessors for the non-sparse version were left dangling. These methods are used by the --kernel and --initrd options, and so those options were just broken. This also fixes a memory leak and refactors the implementation a bit.
2021-01-20add support to page on demand (#634)Chih-Min Chao1-5/+8
This patch splites the target-requested memory regions into pages and only allocates host memory when it is accessed to reduce larget memory sceniaro in 64 bit target system Co-authored-by: Dave.Wen <dave.wen@sifive.com>
2020-05-06Add missing stdexcept importsSchuyler Eldridge1-0/+1
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-15Make CLINT API use Hz instead of MHzAndrew Waterman1-2/+2
2020-02-15Add optional support for real-time clintAnup Patel1-1/+5
This patch adds optional support clint timer incrementing at real-time rate. This can be enabled by passing command line parameter "--real-time-clint". This feature can be used for: 1. Checking whether any code addition to Spike is slowing down simulation too much 2. Comparing run-time for software on Spike with other functional simulators (such as QEMU) Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-07-22Implement MMIO device plugins.Aaron Jones1-0/+14
2018-01-08mem_t: Throw an error if zero-sized memory is requested (#168)Jonathan Neuschäfer1-0/+2
* mem_t: Throw an error if zero-sized memory is requested If for some reason the user requests a memory size of 0 megabytes, print a useful error message. * Check for overflow in memory size If the user passes in a large enough memory size (-m) that the size in bytes doesn't fit into size_t, catch this error in the make_mems function.
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt1-5/+30
2017-05-03Add missing include for devices.hKito Cheng1-0/+2
- https://github.com/riscv/riscv-tools/issues/69
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman1-2/+1
2017-04-30Support more flexible main memory allocationAndrew Waterman1-0/+23
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-5/+8
2016-05-23Have Debug memory kind of working again.Tim Newsome1-6/+0
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Add debug_module bus device.Tim Newsome1-0/+6
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-0/+16
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+34
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