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modes
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HS-mode
The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a
mode other than M-mode. The previous implementation does not check the
permission on accessing vstimecmp in HS-mode. This commit fixes the
issue by moveing the permission check from virtualized_stimecmp_csr_t to
stimecmp_csr_t, which implements the vstimecmp.
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If Smcntrpmf is enabled, mcycle / minstret increment only if counting
for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
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Add Smcsrind / Sscsrind support
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The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0
by adding a specialized class envcfg_csr_t.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
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This adds the following CSRs:
miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353),
mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151),
sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250),
vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257).
Presently, attempts to read / write from ireg? registers will fail, and
future extensions will provide proxy CSR mappings for the respective
?ireg CSRs.
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This change was made ages ago in the spec.
I did not actually test that the new privilege checks in ebreak and
c.ebreak are correct, but all the existing debug tests still pass.
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Resolves #1365
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This commit lets the mstatus.MPP be a valid value if unsupporting
U-mode. Without this commit, the mret may result in a corrupted state
without properly setting the MPP to M-mode (if unsupporting U-mode).
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We don't model any sources of RNMI, so this is mostly vestigial.
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Now, when misa.C is writable, clearing misa.C also disables any
Zc* extension.
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No functional change yet.
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This resolves the issue discussed in #1201.
Prior to 0adf9307, clearing misa.C would disable compressed instructions
and increase IALIGN to 32. Afterwards, clearing misa.C had essentially
no effect because Zca and friends would stay enabled. While AFAICS this
isn't technically incorrect, it certainly doesn't follow the principle
of least surprise.
Instead, remove the feature to toggle misa.C. The effect is that misa.C
is 1 iff C is included in the ISA string, and IALIGN is independent of
misa.C: specifically, IALIGN is 16 iff Zca is present.
(And of course C implies Zca.)
Removing the alignment check on misa writes is not a separate commit
because these two changes should be made atomically. Not checking
the alignment on misa writes goes hand-in-hand with misa.C being
read-only.
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This incurs a negligible performance impact
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chaining
This step is to ensure that removing config.h out of headers will not cause regressions.
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* decode.h contains constants/typedefs/classes. This should not depend on config.h
* decode_macros.h contains internally used macros, and depends on config.h
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misa.H is RW
The masked_csr_t does not meet the behavior of mevent
because the misa.H is not read-only (hardwired).
h/t @kwalker27
reported at https://github.com/riscv-software-src/riscv-isa-sim/pull/1154
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The masked_csr_t does not meet the behavior of mevent
because the misa.H is not read-only (hardwired).
(fix in the next commit)
h/t @kwalker27
reported at https://github.com/riscv-software-src/riscv-isa-sim/pull/1154
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Not very interesting while spike only supports one trigger type,
but #1128 is about to change that. Without tinfo, it can become quite
slow for a debugger to discover which types are supported.
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add suport for jvt: Table entries follow the current data endianness
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add support for sscofpmf extension v0.5.2
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Previously any access to the PMPADDRx CSRs when no PMP regions were
configured would result in an illegal instruction trap, whilst
PMPCFGx registers would act as WARL, ignoring writes and reading as 0.
This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an
illegal instruction trap when accessed when no PMP regions are
configured.
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Illegal instruciton trap should be raised when accessing if related
bit of mcounteren.TM or menvcfg.STCE is zero in VS/VU mode
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since spike doesn't truly support counting of hardware performance events,
only csr related read/write functions is supported currently
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add support for zfinx v1.0
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add stateen related check to frm/fflags
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Hardwire mstatus_fs to zero when enable ZFinx
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Illegal instruciton trap should be raised when accessing senvcfg/
henvcfg/hstateen if related bit of mstateen is zero in VU mode
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Pursuant to https://github.com/riscv-software-src/riscv-isa-sim/issues/668 and https://github.com/riscv-software-src/riscv-isa-sim/issues/194, allowing for additional exceptions to be delegated from M-mode.
It is implementation-defined whether these bits are defined or are read-only-zero.
QEMU implements the added bits (Fetch/Load/StoreAMO access, Load/StoreAMO misalignment, and illegal instruction). (https://github.com/qemu/qemu/blob/f6cce6bcb2ef959cdd4da0e368f7c72045f21d6d/target/riscv/csr.c#L813)
ECALL_FROM_M is not implemented here because it would have no effect, although QEMU does implement it.
This allows Spike to emulate QEMU and other systems which allow for the delegation of such exceptions.
Signed-off-by: Brendan Sweeney <mehnadnerd@gmail.com>
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Update for counter related CSR
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Normally, csrs will reuse the checks in verify_permissions of its base csr type
This modification will not cause any functional change, just reuse the check
in csr_t class to check whether it writes to read-only csr instead of checking
writes to counter_proxy_csr_t by itself.
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add support for m/henvcfgh and mconfigptr CSRs
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