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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-08 18:34:13 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-21 08:50:23 +0800 |
commit | 28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc (patch) | |
tree | d7bcb889ac5757ee84eb2a09a86cbad96c4db18e /riscv/csrs.cc | |
parent | d02b285c8858e33c7f9a79207127c8374c4ddc62 (diff) | |
download | riscv-isa-sim-28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc.zip riscv-isa-sim-28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc.tar.gz riscv-isa-sim-28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc.tar.bz2 |
modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t
Diffstat (limited to 'riscv/csrs.cc')
-rw-r--r-- | riscv/csrs.cc | 34 |
1 files changed, 9 insertions, 25 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6f8f260..9721f87 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -515,6 +515,10 @@ bool rv32_low_csr_t::unlogged_write(const reg_t val) noexcept { return orig->unlogged_write((orig->written_value() >> 32 << 32) | (val & 0xffffffffU)); } +reg_t rv32_low_csr_t::written_value() const noexcept { + return orig->written_value() & 0xffffffffU; +} + // implement class rv32_high_csr_t rv32_high_csr_t::rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): csr_t(proc, addr), @@ -533,6 +537,10 @@ bool rv32_high_csr_t::unlogged_write(const reg_t val) noexcept { return orig->unlogged_write((orig->written_value() << 32 >> 32) | ((val & 0xffffffffU) << 32)); } +reg_t rv32_high_csr_t::written_value() const noexcept { + return (orig->written_value() >> 32) & 0xffffffffU; +} + // implement class sstatus_csr_t sstatus_csr_t::sstatus_csr_t(processor_t* const proc, sstatus_proxy_csr_t_p orig, vsstatus_csr_t_p virt): virtualized_csr_t(proc, orig, virt), @@ -924,10 +932,7 @@ void wide_counter_csr_t::bump(const reg_t howmuch) noexcept { } bool wide_counter_csr_t::unlogged_write(const reg_t val) noexcept { - if (proc->get_xlen() == 32) - this->val = (this->val >> 32 << 32) | (val & 0xffffffffU); - else - this->val = val; + this->val = val; // The ISA mandates that if an instruction writes instret, the write // takes precedence over the increment to instret. However, Spike // unconditionally increments instret after executing an instruction. @@ -941,27 +946,6 @@ reg_t wide_counter_csr_t::written_value() const noexcept { return this->val + 1; } -void wide_counter_csr_t::write_upper_half(const reg_t val) noexcept { - this->val = (val << 32) | (this->val << 32 >> 32); - this->val--; // See comment above. - // Log upper half only. - log_special_write(address + (CSR_MINSTRETH - CSR_MINSTRET), written_value() >> 32); -} - -counter_top_csr_t::counter_top_csr_t(processor_t* const proc, const reg_t addr, wide_counter_csr_t_p parent): - csr_t(proc, addr), - parent(parent) { -} - -reg_t counter_top_csr_t::read() const noexcept { - return parent->read() >> 32; -} - -bool counter_top_csr_t::unlogged_write(const reg_t val) noexcept { - parent->write_upper_half(val); - return true; -} - proxy_csr_t::proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): csr_t(proc, addr), delegate(delegate) { |