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riscv-isa-sim.git
confprec
cs250
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debug_rom
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device_flags
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dts_parsing
dynamic
eos18-bringup
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sifive/rvv0.9-phase2
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csrs.cc
Age
Commit message (
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Author
Files
Lines
2024-05-27
Require vector extension when attempting vxsat writes
rbuchner
1
-0
/
+2
2024-05-01
Remove Zbpbo, Zpn, and Zpsfoperand implementation
Andrew Waterman
1
-2
/
+0
2024-04-29
Merge pull request #1648 from YenHaoChen/pr-hstateen
Andrew Waterman
1
-5
/
+7
2024-04-29
add hlvx pmp protect to fix issue 1557
xinyuwang-sifive
1
-2
/
+2
2024-04-23
Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
YenHaoChen
1
-5
/
+7
2024-04-18
Add Zicfiss extension from CFI extension, v0.4.0
SuHsien Ho
1
-0
/
+10
2024-04-09
Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0
YenHaoChen
1
-0
/
+5
2024-03-22
Allow software check exception to be delegated from M mode regardless of Zicf...
Ming-Yi Lai
1
-1
/
+1
2024-03-06
Zicfilp: Support delegating software check exception handling
Ming-Yi Lai
1
-0
/
+1
2024-03-06
Zicfilp: Preserve expected landing pad state on traps
Ming-Yi Lai
1
-1
/
+3
2024-03-06
Zicfilp: Add CSR fields
Ming-Yi Lai
1
-3
/
+16
2024-02-07
Merge pull request #1591 from YenHaoChen/pr-sstc-stce
Andrew Waterman
1
-2
/
+4
2024-02-06
Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific interr...
YenHaoChen
1
-0
/
+17
2024-02-06
Teach Sstc to respect xenvcfg.STCE
YenHaoChen
1
-2
/
+4
2024-01-10
fix merge issue
Ved Shanbhogue
1
-1
/
+0
2024-01-10
fix merge issue
Ved Shanbhogue
1
-3
/
+0
2024-01-10
Merge branch 'master' into zaamo_zalrsc
Ved Shanbhogue
1
-0
/
+4
2024-01-10
Add Zaamo and Zalrsc extensions
Ved Shanbhogue
1
-1
/
+7
2024-01-10
B=Zba+Zbb+Zbs
Ved Shanbhogue
1
-1
/
+6
2024-01-04
typo: HPM counters consider previous privilege mode if changed
YenHaoChen
1
-1
/
+1
2023-12-30
Add srmcfg CSR
Ved Shanbhogue
1
-0
/
+19
2023-11-29
fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege m...
YenHaoChen
1
-4
/
+4
2023-11-24
stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in H...
YenHaoChen
1
-2
/
+6
2023-07-26
Add Smcntrpmf functionality
Atul Khare
1
-4
/
+43
2023-07-25
Merge pull request #1383 from rivosinc/sscrind_feature
Andrew Waterman
1
-0
/
+62
2023-07-25
legalize henvcfg.CBIE
YenHaoChen
1
-1
/
+1
2023-07-25
legalize senvcfg.CBIE
YenHaoChen
1
-1
/
+1
2023-07-25
legalize menvcfg.CBIE
YenHaoChen
1
-0
/
+13
2023-07-19
Add Smcsrind/Sscsrind support
Atul Khare
1
-0
/
+62
2023-06-01
dscr.ebreakh is now dcsr.ebreakv[su]
Tim Newsome
1
-3
/
+6
2023-05-25
Implement dcsr.v and make DRET use it
Andrew Waterman
1
-1
/
+7
2023-05-25
Use more descriptive variable name in dcsr_csr_t::read; make it reg_t
Andrew Waterman
1
-12
/
+12
2023-05-23
Let mstatus.MPP initially be M-mode if unsupporting U-mode
YenHaoChen
1
-0
/
+1
2023-03-20
Implement Smrnmi extension
Andrew Waterman
1
-0
/
+20
2023-02-15
Disable Zvfh when Zfhmin is disabled
Weiwei Li
1
-1
/
+1
2023-02-15
Disable Zvfh{min} when misa.V is cleared
Weiwei Li
1
-0
/
+2
2023-02-15
Disable Zfh{min} when misa.F is cleared
Weiwei Li
1
-0
/
+2
2023-02-06
Support dynamically disabling misa.C once again
Andrew Waterman
1
-2
/
+15
2023-02-06
Make JVT CSR definition account for dynamically disabling Zcmt
Andrew Waterman
1
-0
/
+3
2023-01-03
Make misa.C read-only
Andrew Waterman
1
-6
/
+1
2022-12-20
Check commitlog-enable dynamicallly for csr_t::log_special_write
Jerry Zhao
1
-4
/
+2
2022-12-15
Add config.h includes directly to source files instead of relying on header c...
Jerry Zhao
1
-0
/
+1
2022-12-15
Split decode.h into public decode.h and private decode_macros.h
Jerry Zhao
1
-1
/
+1
2022-12-09
triggers: implement tdata3 CSR fields
YenHaoChen
1
-2
/
+2
2022-12-09
refactor: add tdata3_csr_t; preparation for CSR textra
YenHaoChen
1
-0
/
+12
2022-12-09
refactor: remove proc parameter from functions of module_t
YenHaoChen
1
-5
/
+5
2022-12-05
clear mevent.VUINH and mevent.VSINH when misa.H is cleared
YenHaoChen
1
-0
/
+4
2022-12-05
add macro N_HPMCOUNTERS (29)
YenHaoChen
1
-1
/
+1
2022-12-05
use extension_enabled('H') instead of extension_enabled_const('H') since misa...
YenHaoChen
1
-1
/
+1
2022-12-05
refactor: add custom CSR class, mevent_csr_t
YenHaoChen
1
-0
/
+12
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