riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-12-11	Merge pull request #1313 from endeneer/fdt-parse-clint-sifive	Jerry Zhao	1	-1/+1
2023-12-11	riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent	Tan En De	1	-1/+1
2023-12-08	Remove cfg_arg_t from cfg_t	Jerry Zhao	1	-1/+1
2023-12-08	Fix Spike --device option to pass on args to downstream plugins	joey0320	1	-1/+2
2023-06-20	device_t: Add device_factory_t's for ns16550/clint/plic	Jerry Zhao	1	-0/+31
2023-06-20	devices: Pass const pointers to sim_t to clint/plic	Jerry Zhao	1	-1/+1
2023-06-20	clint: Change clint_t::increment to override abstract_device_t::tick(rtc_ticks)	Jerry Zhao	1	-5/+5
2023-03-09	Use simif_t instead of sim_t for clint/plic	Scott Johnson	1	-2/+2
2023-03-03	Fix misaligned accesses to clint's msip regs	Scott Johnson	1	-5/+7
2023-03-02	Initialize MTIP at reset	Scott Johnson	1	-0/+1
2023-03-01	Support discontiguous hart IDs in CLINT	Andrew Waterman	1	-30/+47
2022-12-20	Allow reads/writes to reserved CLINT regions	Jerry Zhao	1	-0/+4
2022-07-21	add support for time/timeh/htimedelta/htimedeltah csrs	Weiwei Li	1	-0/+1
2021-09-08	Convert mip to csr_t family	Scott Johnson	1	-5/+5
2020-02-15	Make CLINT API use Hz instead of MHz	Andrew Waterman	1	-3/+3
2020-02-15	Add optional support for real-time clint	Anup Patel	1	-3/+20
2019-11-27	Initialize mtime	Andrew Waterman	1	-1/+1
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	1	-0/+72