riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-06	Add missing stdexcept imports	Schuyler Eldridge	1	-0/+1
2020-04-09	op: update CSR	Chih-Min Chao	1	-2/+2
2020-03-29	When enabling the debug module, poll til it's really enabled	Andrew Waterman	1	-0/+2
2020-03-16	fixed htif exception typo (#423)	Dai chou	1	-1/+1
2020-02-11	FESVR: ensure dmactive is 1 before reading debug module registers	Megan Wachs	1	-3/+3
2020-02-10	FESVR: Can't read a DM register when DMACTIVE=0	Megan Wachs	1	-1/+1
2020-01-31	Merge pull request #390 from jrtc27/payload	Andrew Waterman	2	-8/+37
2020-01-31	Support loading multiple ELF files via a new payload HTIF option	James Clarke	2	-7/+31
2020-01-31	Support plusarg +h/+help option for HTIF	James Clarke	2	-1/+6
2020-01-25	Allow EM_NONE ELFs, too	Andrew Waterman	2	-1/+3
2020-01-25	Refuse to load non-EXEC/non-RISC-V/non-V1 ELFs (#388)	Alexander Lent	2	-0/+10
2019-10-28	Whithhold BE ELF loading until BE target support is available	Marcus Comstedt	1	-9/+3
2019-10-28	Implement support for big-endian hosts	Marcus Comstedt	4	-40/+52
2019-07-05	Add override modifier to fix clang warnings	Andrew Waterman	1	-2/+2
2019-06-14	rvv: add the v-spec-0.7.1 encoding	Chih-Min Chao	1	-1471/+0
2019-03-31	Build fesvr as -fPIC to improve compatibility with old uses	Andrew Waterman	1	-0/+2
2019-03-31	Add fesvr; only globally install fesvr headers/libsstatic-link	Andrew Waterman	34	-0/+6394